Patents by Inventor Vito Dai
Vito Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11714944Abstract: In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics.Type: GrantFiled: December 31, 2020Date of Patent: August 1, 2023Assignee: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Publication number: 20210124865Abstract: In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics.Type: ApplicationFiled: December 31, 2020Publication date: April 29, 2021Applicant: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Ranarajan
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Patent number: 10936778Abstract: In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit.Type: GrantFiled: November 9, 2018Date of Patent: March 2, 2021Assignee: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Patent number: 10339254Abstract: Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.Type: GrantFiled: April 30, 2018Date of Patent: July 2, 2019Assignee: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Publication number: 20190080036Abstract: In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit.Type: ApplicationFiled: November 9, 2018Publication date: March 14, 2019Applicant: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Publication number: 20180247006Abstract: Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.Type: ApplicationFiled: April 30, 2018Publication date: August 30, 2018Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Patent number: 9959380Abstract: Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.Type: GrantFiled: November 4, 2016Date of Patent: May 1, 2018Assignee: Motivo, Inc.Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Publication number: 20170277818Abstract: Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.Type: ApplicationFiled: November 4, 2016Publication date: September 28, 2017Inventors: Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan
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Patent number: 9170501Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.Type: GrantFiled: July 8, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Azat Latypov, Yi Zou, Vito Dai
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Publication number: 20150286763Abstract: Methods and apparatuses for pattern-based methodology for CAA and defect limited yield analysis are disclosed. Embodiments may include matching one or more patterns within a layer of an integrated circuit design layout to one or more pre-characterized patterns within a pattern library, determining respective critical areas of the one or more patterns based on respective pre-characterized critical areas of the one or more pre-characterized patterns, and predicting a defect limited yield of the layer based on the respective pre-characterized critical areas.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Lynn WANG, Sriram MADHAVAN, Vito DAI, Luigi CAPODIECI
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Patent number: 9081919Abstract: System and methods for design-for-manufacturing and design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow are presented. A method includes receiving design data related to layout of an integrated circuit (IC); extracting information from the design data; and performing analysis on the extracted information. The method also enables DFM-DEM aware manufacturing applications using information stored in a knowledge database. The method further updates the knowledge database with new information learned from at least the extracted information and the analysis.Type: GrantFiled: March 13, 2014Date of Patent: July 14, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Vito Dai, Beng Lye Oh, Chiu Wing Hui, Yeow Loye Siew
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Publication number: 20150126032Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: GLOBAL FOUNDRIES, Inc.Inventors: Azat Latypov, Yi Zou, Vito Dai
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Patent number: 9023730Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.Type: GrantFiled: November 5, 2013Date of Patent: May 5, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Azat Latypov, Yi Zou, Vito Dai
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Patent number: 9012270Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.Type: GrantFiled: March 15, 2013Date of Patent: April 21, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Ji Xu, Vito Dai
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Patent number: 9009634Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.Type: GrantFiled: July 8, 2013Date of Patent: April 14, 2015Assignee: GlobalFoundries, Inc.Inventors: Azat Latypov, Yi Zou, Vito Dai
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Publication number: 20150012897Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.Type: ApplicationFiled: July 8, 2013Publication date: January 8, 2015Inventors: Azat Latypov, Yi Zou, Vito Dai
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Publication number: 20150012896Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.Type: ApplicationFiled: July 8, 2013Publication date: January 8, 2015Inventors: Azat Latypov, Yi Zou, Vito Dai
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Patent number: 8924896Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.Type: GrantFiled: January 31, 2013Date of Patent: December 30, 2014Assignee: GlobalFoundries Inc.Inventors: Lynn Wang, Vito Dai, Luigi Capodieci
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Patent number: 8910090Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.Type: GrantFiled: February 27, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Lynn T. Wang, Vito Dai, Luigi Capodieci
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Patent number: 8898606Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.Type: GrantFiled: November 15, 2013Date of Patent: November 25, 2014Assignee: GlobalFoundries Inc.Inventors: Rani Abou Ghaida, Ahmed Mohyeldin, Piyush Pathak, Swamy Muddu, Vito Dai, Luigi Capodieci