Patents by Inventor Vito Raineri

Vito Raineri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060183267
    Abstract: A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the surface of the epitaxial layer for forming a modified intermediate layer of at least one surface portion of the epitaxial layer for making the electric behavior of the interface region substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer.
    Type: Application
    Filed: September 27, 2005
    Publication date: August 17, 2006
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fabrizio Roccaforte, Vito Raineri, Francesco La Via, Mario Saggio
  • Patent number: 6762112
    Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: July 13, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vito Raineri, Mario Saggio
  • Patent number: 6709955
    Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: March 23, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Saggio, Vito Raineri, Umberto Stagnitti, Sebastiano Mugavero
  • Publication number: 20030003680
    Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.
    Type: Application
    Filed: February 20, 2002
    Publication date: January 2, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Vito Raineri, Mario Saggio
  • Patent number: 6451672
    Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: September 17, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Caruso, Vito Raineri, Mario Saggio, Umberto Stagnitti
  • Publication number: 20020001923
    Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.
    Type: Application
    Filed: April 27, 2001
    Publication date: January 3, 2002
    Inventors: Mario Saggio, Vito Raineri, Umberto Stagnitti, Sebastiano Mugavero
  • Patent number: 6168981
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 2, 2001
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 5900652
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: May 4, 1999
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 5723372
    Abstract: A method and apparatus for forming buried oxide layers within silicon wafers comprising several steps. Recesses are formed in a silicon wafer. Light ions are implanted in the silicon wafer at a depth that is smaller than the depth of the recesses to form bubbles of the light ions in the silicon wafer. The light ions are evaporated from the silicon wafer to leave cavities in the place of the bubbles. The cavities are oxidized through the recesses to form a buried layer of silicon oxide.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: March 3, 1998
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Salvatore Ugo Campisano, Vito Raineri