Abstract: In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed.

Abstract: In some embodiments, a stacked package assembly may include a first socket defining an interior cavity, a first semiconductor device coupled to the first socket, a second socket positioned within the interior cavity of the first socket, and a second semiconductor device removably coupled to the second socket within the cavity of the first socket. The second socket may be positioned between the first semiconductor device and the second semiconductor device and provide an electrical connection between the first semiconductor device and the second semiconductor device. Other embodiments are disclosed and claimed.

Abstract: Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server.

Abstract: In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed.

Abstract: Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server.

Abstract: According to some embodiments, it may be determined that a processing system is to transition from a higher-power state to a lower-power state. System information may then be copied from a volatile memory device to a low-latency persistent memory device, and it may be arranged for the processing system to transition from the higher-power state to the lower-power state.

Abstract: In some embodiments, a device includes an electronic privacy filter. Other embodiments are disclosed and claimed.

Abstract: Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server.

Abstract: Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server.

Abstract: Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server.

Abstract: A panel controller is brought closer to the graphics controller and other components of the video subsystem. The panel controller is reconfigurable, such as by parameters received from the display panel, and is thus useable with multiple different species of display panel.

Abstract: An apparatus and method for monitoring and controlling the internal state of a computer system, in particular, a computer server. The computer system includes one or more subsystems. These subsystems provide one or more management signals at a system management slot. The computer system also includes an I/O bus slot coupled to an I/O bus of the computer system. A system management agent is coupled to both the system management slot and the I/O bus slot. The system management agent includes a processor and a memory system coupled to the processor. The system management agent also includes a communications interface coupled to the processor and the memory system.

Abstract: A system instrumentation driver, a subsystem instrumentation interface, and a number of subsystem instrumentation handlers, are provided to a computer system platform for accessing system management features and functions of the platform. The system instrumentation driver is operating system specific; it is used to issue subsystem commands to the subsystem instrumentation interface, in response to system management calls from system management agent software. The subsystem instrumentation interface is platform, operating system as well as subsystem implementation independent; it is used to map each subsystem command into one or more invocations of the appropriate subsystem instrumentation handlers. The subsystem instrumentation handlers are platform and subsystem specific; they are used to access the vadous system management features and functions of the platform.

Abstract: A functional-redundancy checking logic for checking identical chips whose outputs are time-variant programmable. Window logic (40, 60) on each chip creates a window associated with each programmed transition, set pulse (14) and reset pulse (15). For the set pulse (14), on the rising edge (42) of the window, an error flip-flop (50) is set. The flip-flop is merely set at this time; an error is not flagged. The window remains open for a fixed time period. During the time period that the window is open, if the output pin (24) is ever correctly asserted, then the flip-flop (50) is reset, thus clearing the error flag. However, if the pin (24) always remains incorrectly asserted, indicating an error, then the error flip-flop (50) remains set. When the window closes on the falling edge (46) of the window pulse, an error report pulse is created via the AND (52). The value on the flip-flop (50) at this time is reported as an error (54). An identical circuit checks the programmable reset pulse ( 15).

Abstract: In order for any failure of the power supply unit for two read-write memories which are operable in parallel, not to result in irreversible damage to data, two parallel power supply circuits are provided for the operation of the memories. Each power supply circuit is capable of supplying the operating current of one of the memories and the standby current of the remaining memory. Each of the power supply circuits in the power supply is buffered with capacitors in such a manner that, upon a fault in one of the power supply circuits, the output voltage, as soon as the capacitive buffer declines from a normal operating voltage to a threshold voltage and to a minimum operating voltage, data secure current reducing steps are taken.

Abstract: The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3.