Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

Abstract: A communications device includes a communication receiver. The communications receiver is configured to receive a message with location information, determine the location of the communication device, and output the message only when the communication device is within the location specified by the location information.

Abstract: A Specific Location Space Communication System which provides information to subscriber as function of their location and group memberships. A receiver device gets messages from space and/or aerial communication station which are selectively passed to the subscriber based on set parameters in the receiver message and more. Further, the receiver devices with transmitting capability can provide status, location and memory data to multitude of terrestrial, aerial and space based receivers. Further, the received message is classified in to an emergency alert message, advertising message, commerce message, control message etc.

Abstract: A broadcast system for consolidating and broadcasting the information from a broadcast server to the specific location and a communication receiver configured to receive broadcast message, determine the location of the communication receiver, and output the message to the communication device when the communication receiver is within the location specified in the received message or when the received message matches one or more criteria associated with configuration or location or unique address of the communication device. The communication receiver provides means of collecting information from the communication device and the communication device operator and presenting it to the message broadcasting entity.