Abstract: An IF sampling receiver for use in a wireless communication system includes first and second channels, with one channel generating an in-phase (I) component of an incoming analog IF signal, and the other channel generating a quadrature (Q) component of the analog IF signal. Each of the two channels of the IF sampling receiver includes a corresponding sigma-delta modulator channel. Each of the two sigma-delta modulator channels may be separated into m parallel branches by applying a polyphase decomposition technique to one or more resonators associated with the sigma-delta modulator. The invention thus provides a general framework for configuring a given channel of a sigma-delta modulator to include m parallel branches. The invention also provides a technique for separating a given sigma-delta modulator into n parallel channels, where n is greater than 2. Each of the n parallel channels may then be separated into m parallel branches.

Abstract: A tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter. A decoder converts the RC product as measured by the A/D converter into a digital code which, when applied to the appropriate capacitor array, sets the array capacitance to compensate for the difference between the measured RC product and the nominal design value.

Abstract: A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.

Abstract: Temperature and technology-independent self-calibrating monolithic logarithmic amplifier systems that use integrated cascades of current-summing or voltage-summing differential-limiter gain stages are disclosed. Each stage is trimmed and stabilized by a respective bias replicator cell and a current mirror cell. The bias replicator provides a bias current control signal in response to a change in a given difference between bias currents in a differential pair of amplifiers controlled by a predetermined differential calibration voltage. The differential pair is identical to a differential pair in the limiter amplifier. The differential calibration voltage E.sub.lin is well-within the linear portion of the amplifier's transfer curve during operation, so that the proportional relation between E.sub.k and E.sub.lin, which is the same as that between the given difference between currents and the correct bias current value I.sub.B, remains constant throughout.

Abstract: DC offset cancellation and timing recovery is provided in a homodyne receiver. The homodyne receiver demodulates an RF signal to produce a baseband signal. An initial offset correction module determines an initial DC offset of the baseband signal. An initial offset correction is applied to the baseband signal to provide an initial corrected baseband signal. Wherein, a dynamic DC offset correction module determines a dynamic DC offset. A dynamic DC offset correction is applied to the initial corrected baseband signal providing a dynamic corrected baseband signal. A timing signal is acquired from the baseband signal for synchronizing the receiver to a transmitter. A method for correcting DC offset of a baseband signal in a homodyne receiver is also described.

Abstract: A telephone circuit which may be monolithically integrated, for generating control signals for displaying the telephone charges to a telephone user, is coupled to a AC voltage signal generator having a predetermined amplitude and frequency which are constant over time. The circuit includes a voltage generator for generating voltage signals which are spaced over time and have a trapezoidal pulse waveshape. A multiplier circuit calculates the product of the signals supplied by the two generators and supplies a signal which is sent to the speech circuit of the subscriber's line and is added to the speech (i.e.--conversation) signals. The circuit also includes a circuit for receiving an image signal of the overall signal adapted to the telephone line; a high-pass filter for eliminating the speech signal components from the image signal; a rectifier circuit for rectifying the filtered signal and a comparator for comparing the rectified signal with a reference signal.