Patents by Inventor Vivek Amir Jairazbhoy
Vivek Amir Jairazbhoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10396411Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a battery cell array having a plurality of battery cells. A thermal plate may be positioned beneath the battery cells and be configured for thermal communication therewith. The thermal plate may define a plurality of channel configurations within the thermal plate. Each of the channel configurations may correspond to one of the battery cells and include an inlet and outlet on a same side portion of the thermal plate. An inlet plenum may be in communication with the inlets and an outlet plenum may be in communication with the outlets. The channel configurations and plenums may be arranged such that fluid exiting the inlet plenum enters the channel configurations via the outlets and fluid exiting the outlets enters the outlet plenum and not into the inlet of another one of the channel configurations.Type: GrantFiled: February 25, 2014Date of Patent: August 27, 2019Assignee: FORD GLOBAL TECHNOLOGIES, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows
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Patent number: 9452683Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a battery cell array and a thermal plate configured to support the battery cell array. The thermal plate may define an inlet port, two outer channels each having a channel inlet in communication with the inlet port, at least three inner channels disposed between the outer channels, and an outlet port. The ports and channels may be arranged such that fluid traveling through any two adjacent channels flows in opposite directions and fluid, when exiting the thermal plate, empties from one or more of the inner channels into the outlet port without first entering the channel inlets.Type: GrantFiled: February 25, 2014Date of Patent: September 27, 2016Assignee: Ford Global Technologies, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows
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Patent number: 9368845Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a plurality of battery cells and a thermal plate positioned beneath the battery cells. The thermal plate may be configured for thermal communication with the plurality of battery cells. The thermal plate may define a plurality of multi-pass channel configurations, each corresponding to one of the battery cells. The multi-pass channel configurations may each include a channel inlet and channel outlet on opposite side portions of the thermal plate. The multi-pass channel configurations may each be configured to direct thermal fluid flowing therein to an outlet port of the thermal plate without directing fluid to the channel inlet of another channel configuration.Type: GrantFiled: February 25, 2014Date of Patent: June 14, 2016Assignee: Ford Global Technologies, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows, LeeAnn Wang
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Publication number: 20150244038Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a plurality of battery cells and a thermal plate positioned beneath the battery cells. The thermal plate may be configured for thermal communication with the plurality of battery cells. The thermal plate may define a plurality of multi-pass channel configurations, each corresponding to one of the battery cells. The multi-pass channel configurations may each include a channel inlet and channel outlet on opposite side portions of the thermal plate. The multi-pass channel configurations may each be configured to direct thermal fluid flowing therein to an outlet port of the thermal plate without directing fluid to the channel inlet of another channel configuration.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: Ford Global Technologies, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows, LeeAnn Wang
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Publication number: 20150244039Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a battery cell array having a plurality of battery cells. A thermal plate may be positioned beneath the battery cells and be configured for thermal communication therewith. The thermal plate may define a plurality of channel configurations within the thermal plate. Each of the channel configurations may correspond to one of the battery cells and include an inlet and outlet on a same side portion of the thermal plate. An inlet plenum may be in communication with the inlets and an outlet plenum may be in communication with the outlets. The channel configurations and plenums may be arranged such that fluid exiting the inlet plenum enters the channel configurations via the outlets and fluid exiting the outlets enters the outlet plenum and not into the inlet of another one of the channel configurations.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: Ford Global Technologies, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows
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Publication number: 20150244037Abstract: A traction battery assembly for a vehicle is provided. The traction battery assembly may include a battery cell array and a thermal plate configured to support the battery cell array. The thermal plate may define an inlet port, two outer channels each having a channel inlet in communication with the inlet port, at least three inner channels disposed between the outer channels, and an outlet port. The ports and channels may be arranged such that fluid traveling through any two adjacent channels flows in opposite directions and fluid, when exiting the thermal plate, empties from one or more of the inner channels into the outlet port without first entering the channel inlets.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: FORD GLOBAL TECHNOLOGIES, LLCInventors: Vivek Amir Jairazbhoy, George Albert Garfinkel, Neil Robert Burrows
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Publication number: 20080266820Abstract: A system for supporting and electrically grounding metallic covers for electronic control modules includes a housing having wall portions defining a cavity with an opening, a circuit board located within the cavity, the circuit board having a ground plane formed within the circuit board, the circuit board having a top surface substantially facing the opening and supports for proving structural support for the cover, the supports being located on the top surface of the circuit board. The system shields emissions radiating from the module.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Inventors: Vivek Amir Jairazbhoy, Diane Marie Jett, Bertrand Robert Mohr, Robert Edward Belke, Michael Timothy Dwyer
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Patent number: 6826829Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes fixing the die to the substrate, interconnecting the electronic die to an at least one bonding pad on the substrate to form an electrical connection, coating the interconnects and the electronic die with an electrically insulating coating, and covering the electronic die with a low temperature melting metal. Thus, the method of the present invention improves the reliability of the electronic die.Type: GrantFiled: March 7, 2002Date of Patent: December 7, 2004Assignee: Visteon Global Technologies, Inc.Inventors: Cuong Van Pham, Jay DeAvis Baker, Mohan R. Paruchuri, Prathap Amervai Reddy, Vivek Amir Jairazbhoy
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Publication number: 20030167630Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes fixing the die to the substrate, interconnecting the electronic die to an at least one bonding pad on the substrate to form an electrical connection, coating the interconnects and the electronic die with an electrically insulating coating, and covering the electronic die with a low temperature melting metal. Thus, the method of the present invention improves the reliability of the electronic die.Type: ApplicationFiled: March 7, 2002Publication date: September 11, 2003Inventors: Cuong Van Pham, Jay DeAvis Baker, Mohan R. Paruchuri, Prathap Amervai Reddy, Vivek Amir Jairazbhoy
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Patent number: 6601753Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes depositing a pad of low temperature die attachment material within a die attachment area on the substrate, positioning the die over the pad of low temperature die attachment material, and compressing the die against the substrate to expel air trapped within the pad of low temperature die attachment material. Further, a bead of containment material is deposited onto the substrate to define the die attachment area. In this manner, the die attachment material is contained on the substrate. Thus, the method of the present invention improves the reliability of the electronic die.Type: GrantFiled: May 17, 2001Date of Patent: August 5, 2003Assignee: Visteon Global Technologies, Inc.Inventors: Jay DeAvis Baker, Lawrence Leroy Kneisel, Mohan R. Paruchuri, Prathap Amervai Reddy, Vivek Amir Jairazbhoy
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Patent number: 6584682Abstract: A method 10 for making multi-layer electronic circuit boards 148, 248 having aperture 146, 246 which may be selectively connected to an electrical ground potential.Type: GrantFiled: March 20, 2001Date of Patent: July 1, 2003Assignee: Visteon Global Tech., Inc.Inventors: Robert Edward Belke, Thomas Bernd Krautheim, Vivek Amir Jairazbhoy, Delin Li
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Publication number: 20020170944Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes depositing a pad of low temperature die attachment material within a die attachment area on the substrate, positioning the die over the pad of low temperature die attachment material, and compressing the die against the substrate to expel air trapped within the pad of low temperature die attachment material. Further, a bead of containment material is deposited onto the substrate to define the die attachment area. In this manner, the die attachment material is contained on the substrate. Thus, the method of the present invention improves the reliability of the electronic die.Type: ApplicationFiled: May 17, 2001Publication date: November 21, 2002Inventors: Jay DeAvis Baker, Lawrence Leroy Kneisel, Mohan R. Paruchuri, Prathap Amervai Reddy, Vivek Amir Jairazbhoy
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Publication number: 20020144802Abstract: A container defines an annular chamber that is partially filled with a liquid coolant. The container is capable of receiving a cooling conduit in which forced air or liquid flows. Heat generated by an electronic device is transferred to the liquid coolant within the container and causes the liquid coolant to boil. The vaporized coolant rises away from the electronic device carrying the latent heat of vaporization. The vaporized coolant condenses on and near surfaces within the container cooled by the cooling conduit and the heat is transferred to the air or liquid within the cooling conduit. The condensed coolant travels back toward the electronic device via gravity and/or a wick structure.Type: ApplicationFiled: April 6, 2001Publication date: October 10, 2002Applicant: VISTEON GLOBAL TECHNOLOGIESInventors: Vivek Amir Jairazbhoy, Prathap Amervai Reddy, Jay D. Baker, Lawrence LeRoy Kneisel, Myron Lemecha
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Patent number: 6449839Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.Type: GrantFiled: September 6, 2000Date of Patent: September 17, 2002Assignee: Visteon Global Tech., Inc.Inventors: Andrew Z. Glovatsky, Thomas Krautheim, Robert E. Belke, Jr., Vivek Amir Jairazbhoy, Cuong V. Pham
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Patent number: 6405920Abstract: There is disclosed herein a printed circuit board (PCB) having enhanced mounting pads useful for overprinting solder paste and for repair of the solder joints. The PCB comprises: a dielectric substrate 10 having at least one mounting pad 20 thereon, wherein each mounting pad is arranged in matched relation with a respective termination 32 of an electronic component 30. Each mounting pad 20 includes a main body portion 24 and one or more fingerlike extensions 26 extending outward from the main body portion and away from a projected footprint 34 of the electronic component.Type: GrantFiled: July 12, 2000Date of Patent: June 18, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Bjoern Erik Brunner, Vivek Amir Jairazbhoy, Richard Keith McMillan
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Patent number: 6395087Abstract: A novel apparatus for compressing viscous material through openings in a stencil is disclosed. The novel apparatus has a compress on head cap which provides a contained environment to direct and to aid the flow of pressurized viscous material through the openings in the stencil. In another embodiment of the invention, the compression head includes a viscous material reception chamber which has a certain shape which is effective to cause said received viscous material to be selectively dispensed while having a substantially uniform velocity profile and which further provides for the creation of a substantially uniform pressure profile.Type: GrantFiled: July 22, 1999Date of Patent: May 28, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Vivek Amir Jairazbhoy, Jeff (Jin Her) Lin, John Trublowski, Vinh Van Ha, Zhaoji Yang
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Patent number: 6391211Abstract: A method for making multi-layer electronic circuit board including a pre-circuit assembly 12 and a ground layer 14 which are automatically aligned and bonded together by use of solder material or deposits 26, 28.Type: GrantFiled: September 6, 2000Date of Patent: May 21, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Andrew Z. Glovatsky, Robert Joseph Gordon, Vivek Amir Jairazbhoy, Vladimir Stoica
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Patent number: 6381837Abstract: A method for producing an electronic circuit assembly (e.g., a circuit board) from an etched tri-metal-layer structure which provides air bridge crossovers and specially designed bumps etched from a middle layer of the tri-metal-layer structure. The bumps are formed at particular circuit locations in order to provide interconnects for (1) heavy wirebonding, (2) fine wirebonding, or (3) direct chip attachment; or, to provide (4) lifters for assuring a minimum solder joint standoff height or (5) barriers for retarding solder joint crack propagation.Type: GrantFiled: September 4, 1998Date of Patent: May 7, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Jay DeAvis Baker, Edward McLeskey, Delin Li, Cuong Van Pham, Robert Edward Belke, Vivek Amir Jairazbhoy, Thomas B Krautheim, Mohan R. Paruchuri, Lakhi Nandlal Goenka, Jun Ming Hu
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Patent number: 6361606Abstract: A novel apparatus for compressing viscous material through openings in a stencil is disclosed. The novel apparatus has a compression head cap which provides a contained environment to direct and to aid the flow of pressurized viscous material through the openings in the stencil. In another embodiment of the invention, the compression head includes a selectively expandable diaphragm and viscous material reception and dispensation apertures. The viscous material reception aperture is formed in close proximity to the material dispensation aperture and this aperture placement to allow the viscous material to be selectively dispensed with a substantially uniform velocity and pressure profile. In another embodiment, the compression head includes a selectively expandable diaphragm which further increases the uniformity of the velocity and pressure profiles.Type: GrantFiled: July 22, 1999Date of Patent: March 26, 2002Assignee: Visteon Global Tech., Inc.Inventor: Vivek Amir Jairazbhoy
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Publication number: 20020020552Abstract: A method 10 for making multi-layer electronic circuit boards 148, 248 having aperture 146, 246 which may be selectively connected to an electrical ground potential.Type: ApplicationFiled: March 20, 2001Publication date: February 21, 2002Inventors: Robert Edward Belke, Thomas Bernd Krautheim, Vivek Amir Jairazbhoy, Delin Li