Abstract: A system that enables searching for representing listings for accommodation reservations on a map is described. The system receives, by a network site of a listing network platform, input comprising search criteria associated with a geographical region and identifies a plurality of listings matching the search criteria. The system identifies a first subset listings of the plurality of listings that is each associated with a respective location that is within a boundary associated with the geographical region and a second subset listings of the plurality of listings that is each associated with a respective location that is outside the boundary associated with the geographical region. The system visually distinguishes the first subset of listings from the second subset of listings on a map-based graphical user interface (GUI) that represents the plurality of listings matching the search criteria.

Abstract: A system that enables searching for listings for accommodation reservations is described. The system receives, by a network site of a listing network platform, input comprising search criteria and identifies a plurality of listings matching the search criteria. The system generates a graphical user interface comprising a plurality of graphical objects each associated with a respective one of the identified plurality of listings. The system determines that the search criteria satisfies an amenity criterion and, in response, causes one or more amenities associated with an individual listing of the identified plurality of listings to be presented in an individual graphical object of the plurality of graphical objects associated with the individual listing.

Abstract: A system that enables searching for representing listings for accommodation reservations on a map is described. The system receives, by a network site of a listing network platform, input comprising search criteria associated with a geographical region and identifies a plurality of listings matching the search criteria. The system identifies a first subset listings of the plurality of listings that is each associated with a respective location that is within a boundary associated with the geographical region and a second subset listings of the plurality of listings that is each associated with a respective location that is outside the boundary associated with the geographical region. The system visually distinguishes the first subset of listings from the second subset of listings on a map-based graphical user interface (GUI) that represents the plurality of listings matching the search criteria.

Abstract: Data is received that includes a data set characterizing a plurality of insurance provider profiles and/or claims. Thereafter, a minimum volume ellipsoid is determined for the data set. Subsequently, at least one provider profile and/or claim is identified having at least one outlier variable based on a distance that the at least one provider profile and/or claim has relative to a center point of the minimum volume ellipsoid. Data is then provided (e.g., displayed, stored, loaded into memory, transmitted to a remote computing system, etc.) that characterizes the at least one provider profile and/or claim as likely being fraudulent or erroneous. In other variations, the minimum volume ellipsoid is determined using a different data set. Related apparatus, systems, techniques and articles are also described.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: A scoring model is provided that is trained using historical patient readmission data. The scoring model is used to analyze patient insurance claim data for which patients were readmitted to a healthcare facility in order to characterize whether the corresponding insurance claims are potentially fraudulent or erroneous. Related techniques, apparatus, systems, and articles are also described.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.