Abstract: This application discloses a computing system to identify portions of source code in a test bench that correspond to class objects, and insert handle tracking code at locations in the test bench associated with the identified portions of source code. During simulation of the test bench, the computing system can execute the handle tracking code, which generates handle occupancies corresponding to memory pointers associated with the class objects. Each of the handle occupancies can include a handle reference or memory pointer for a class object, a location in the test bench corresponding to usage of the memory pointer, and a simulation time associated with the generation of the handle occupancy. The computing system can arrange the handle occupancies, synchronize the handle occupancies to portions of source code in the test bench, and display the handle occupancies and the test bench source code in a debug window.

Abstract: This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

Abstract: This application discloses a computing system to identify portions of source code in a test bench that correspond to class objects, and insert handle tracking code at locations in the test bench associated with the identified portions of source code. During simulation of the test bench, the computing system can execute the handle tracking code, which generates handle occupancies corresponding to memory pointers associated with the class objects. Each of the handle occupancies can include a handle reference or memory pointer for a class object, a location in the test bench corresponding to usage of the memory pointer, and a simulation time associated with the generation of the handle occupancy. The computing system can arrange the handle occupancies, synchronize the handle occupancies to portions of source code in the test bench, and display the handle occupancies and the test bench source code in a debug window.

Abstract: This application discloses a debug tool to prompting display of at least a portion of a simulated output for a circuit design in a debug window, identifying a marker corresponding to a value in the simulated output has been specified for the debug environment, and prompting accentuation of one or more occurrences of the value in the debug window relative to other values in the simulated output based, at least in part, on the marker specified for the debug environment.

Abstract: This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.

Abstract: This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.

Abstract: This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.

Abstract: This application discloses a debug tool to prompting display of at least a portion of a simulated output for a circuit design in a debug window, identifying a marker corresponding to a value in the simulated output has been specified for the debug environment, and prompting accentuation of one or more occurrences of the value in the debug window relative to other values in the simulated output based, at least in part, on the marker specified for the debug environment.

Abstract: This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.