Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for analyzing the test vectors to quickly and accurately calculate the switching activity at each test clock pulse or scan cycle. According to some approaches, load vector data and unload vector data are analyzed to determine toggle counts and switching activity, without requiring simulation to be performed.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

Abstract: A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a nonlinear gating signal using a first set of outputs and a data value feeding one or more scan chains of the spreader network using a second set of outputs. The pipeline clock of a pipeline element of the scan chains is gated using the nonlinear gating signal, and the data value is fed to the scan chains based on the pipeline clock. The scan chains are fed with updated values at the pipeline stage.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: Various embodiments of the present invention provide for automated synthesizing of a circuit wrapper for an integrated circuit element. Specifically, some embodiments of the invention provide computer-aided design (CAD) support for automated circuit wrapper generation, especially circuit test wrappers. Additionally, various embodiments of the invention result in optimally designed and segmented circuit wrappers that are configured for both parallel instruction mode and serial instruction mode.

Abstract: A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.