Abstract: Techniques described herein focus on resource sharing (e.g., sharing of some communication buses) and intelligent routing of data between a source device and multiple destination devices to improve data transfer efficiency. For example, the techniques proposed herein describe the use of a combination of merged pipeline communication buses and separate pipeline communication buses for transfer of the data between the source device and the multiple destination devices.

Abstract: A method for time borrowing in memory timing paths of a memory is described. The method includes holding memory input data in a latch buffer according to a core clock. The method also includes delaying the core clock to generate a memory clock. The method further includes feeding the memory input data from the latch buffer to a memory input of the memory according to the memory clock. The method also includes accessing a memory output of the memory according to the core clock.

Abstract: A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.

Abstract: A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.