Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Abstract: This disclosure generally relates to a method and system for providing a ride for a third party rider at the request of a user ride requestor. In one embodiment, a driver device may be used to receive a ride request from one or more server computing devices for a third party rider. The driver device may receive information identifying the third party rider, including a password. Further, the driver device may transmit real time ride status information to the ride requestor directly or indirectly via the one or more server computing devices.

Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract: This disclosure covers methods, non-transitory computer readable media, and systems that receive a direct digital message for delivery to a recipient and then generate a relevance score representing the direct digital message's relevance to the recipient. The relevance score accounts for either or both of crowdsourced information and social-network signals. Based on the relevance score, the methods, non-transitory computer readable media, and systems either provide the direct digital message to the recipient's client device for display within a received-messages preview or provide the message to the recipient's client device for sequestration within a sequestration folder.

Abstract: This disclosure covers methods, non-transitory computer readable media, and systems that analyze a previously unrecognized communication number associated with a sender of a direct digital message when a client device receives the direct digital message from the previously unrecognized communication number. Based on this analysis, the methods, non-transitory computer readable media, and systems provide profile information associated with the communication number for the client device to present together with the direct digital message. To find relevant profile information for the communication number, the disclosed methods, non-transitory computer readable media, and systems optionally query a social networking system for profile information connected to the communication number.

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

Abstract: In an example method, a mobile device obtains a signal indicating an acceleration measured by a sensor over a time period. The mobile device determines an impact experienced by the user based on the signal. The mobile device also determines, based on the signal, one or more first motion characteristics of the user during a time prior to the impact, and one or more second motion characteristics of the user during a time after the impact. The mobile device determines that the user has fallen based on the impact, the one or more first motion characteristics of the user, and the one or more second motion characteristics of the user, and in response, generates a notification indicating that the user has fallen.

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract: At least one ALM artifact, indexed by a unified data store, that does not comply with at least one process convention can be identified. Responsive to identifying the ALM artifact, indexed by the unified data store, that does not comply with the process convention, a determination can be made by a process convention agent executed by a processor as to whether script code is available to update the ALM artifact to comply with the process convention. Responsive to the process convention agent determining that script code is available to update the ALM artifact to comply with the process convention, the process convention agent can automatically execute the script code to update the ALM artifact to comply with the process convention.

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract: This disclosure generally relates to a method and system for providing a ride for a third party rider at the request of a user ride requestor. In one embodiment, a driver device may be used to receive a ride request from one or more server computing devices for a third party rider. The driver device may receive information identifying the third party rider, including a password. Further, the driver device may transmit real time ride status information to the ride requestor directly or indirectly via the one or more server computing devices.

Abstract: At least one ALM artifact, indexed by a unified data store, that does not comply with at least one process convention can be identified. Responsive to identifying the ALM artifact, indexed by the unified data store, that does not comply with the process convention, a determination can be made by a process convention agent executed by a processor as to whether script code is available to update the ALM artifact to comply with the process convention. Responsive to the process convention agent determining that script code is available to update the ALM artifact to comply with the process convention, the process convention agent can automatically execute the script code to update the ALM artifact to comply with the process convention.

Abstract: At least one ALM artifact, indexed by a unified data store, that does not comply with at least one process convention can be identified. Responsive to identifying the ALM artifact, indexed by the unified data store, that does not comply with the process convention, a determination can be made by a process convention agent executed by a processor as to whether script code is available to update the ALM artifact to comply with the process convention. Responsive to the process convention agent determining that script code is available to update the ALM artifact to comply with the process convention, the process convention agent can automatically execute the script code to update the ALM artifact to comply with the process convention.

Abstract: This disclosure generally relates to a method and system for providing a ride for a third party rider at the request of a user ride requestor. In one embodiment, a driver device may be used to receive a ride request from one or more server computing devices for a third party rider. The driver device may receive information identifying the third party rider, including a password. Further, the driver device may transmit real time ride status information to the ride requestor directly or indirectly via the one or more server computing devices.

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.