Patents by Inventor Vivek Kishorechand Arora
Vivek Kishorechand Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250087591Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.Type: ApplicationFiled: November 26, 2024Publication date: March 13, 2025Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
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Publication number: 20250022782Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Inventors: Woochan Kim, Vivek Kishorechand Arora
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Patent number: 12154861Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.Type: GrantFiled: October 31, 2019Date of Patent: November 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
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Patent number: 12136588Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.Type: GrantFiled: July 19, 2021Date of Patent: November 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Vivek Kishorechand Arora
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Patent number: 12125799Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.Type: GrantFiled: November 2, 2021Date of Patent: October 22, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
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Publication number: 20240258245Abstract: An electronic device that includes a substrate and a die disposed on the substrate, the die having an active surface. Wire bonds are attached from the active surface of the die to the substrate. A radiation barrier is attached to the substrate and disposed over the die. The radiation barrier is configured to mitigate electromagnetic radiation exposure to the die. A mold compound is formed over the die, the wire bonds, and the radiation barrier.Type: ApplicationFiled: January 26, 2023Publication date: August 1, 2024Inventors: KWANG-SOO KIM, WOOCHAN KIM, VIVEK KISHORECHAND ARORA
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Patent number: 11923281Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.Type: GrantFiled: April 12, 2022Date of Patent: March 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anindya Poddar, Woochan Kim, Vivek Kishorechand Arora
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Patent number: 11869839Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.Type: GrantFiled: May 11, 2021Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Benjamin Allen Samples, Vivek Kishorechand Arora
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Publication number: 20230413467Abstract: A power conversion module and method of forming the same includes a motherboard having a first surface and a second surface that opposes the first surface. The motherboard includes a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard and an output node of a power conversion module. The motherboard includes a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node and a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor. The power module includes a first daughterboard mounted on the first surface of the motherboard and a second daughterboard mounted on the second surface of the motherboard.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Woochan Kim, Vivek Kishorechand Arora, David Ryan Huitink, Hayden Seth Carlton, Fang Luo, Asif Imran Emon
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Publication number: 20230395514Abstract: An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Kwnag-Soo Kim, Vivek Kishorechand Arora, Woochan Kim
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Publication number: 20230386963Abstract: A power converter module includes a substrate having a first surface and a second surface that opposes the first surface. The power converter module includes a thick printed copper (TPC) substrate on the first surface of the substrate. The TPC substrate includes a first layer having TPC patterned on the first surface of the substrate and a second layer with dielectric patterned on the first layer. The TPC substrate includes a third layer having TPC patterned on the second layer. The power converter module includes power transistors mounted on the TPC substrate and a control integrated circuit (IC) chip mounted on the TPC substrate.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: WOOCHAN KIM, Vivek Kishorechand Arora, Ninad Shahane, Makoto Shibuya
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Publication number: 20230378022Abstract: A power module includes an interconnect of an integrated circuit (IC) package having a heat slug. The power module also includes a direct bonded copper (DBC) substrate. The DBC substrate has a first surface formed of pattern copper, the patterned copper has a pad and a second surface that opposes the first surface, the second surface has a sheet of copper. The second surface of the DBC substrate is thermally coupled to the heat slug. The power module further includes a die mounted on the pad of the first surface of the DBC substrate. The die has a power transistor. The die and the heat slug are thermally coupled and electrically isolated.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: KWANG-SOO KIM, Vivek Kishorechand Arora, Woochan Kim
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Publication number: 20230378034Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Woochan Kim, Vivek Kishorechand Arora
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Publication number: 20230307314Abstract: A semiconductor device includes a direct bonded copper (DBC) substrate including a plurality of indentations in at least a top side of a ceramic substrate. The plurality of indentations are filled with a metal filler to provide metal filled dimples. A top copper layer is a patterned layer that is on the top side and provides leads, and there is at least one semiconductor die having bond pads electrically connected to the leads.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Kwnag-Soo Kim, Makoto Shibuya, Vivek Kishorechand Arora
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Patent number: 11751353Abstract: A power conversion module and method of forming the same includes a motherboard having a first surface and a second surface that opposes the first surface. The motherboard includes a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard and an output node of a power conversion module. The motherboard includes a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node and a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor. The power module includes a first daughterboard mounted on the first surface of the motherboard and a second daughterboard mounted on the second surface of the motherboard.Type: GrantFiled: May 12, 2021Date of Patent: September 5, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Vivek Kishorechand Arora, David Ryan Huitink, Hayden Seth Carlton, Fang Luo, Asif Imran Emon
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Patent number: 11715679Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.Type: GrantFiled: October 9, 2019Date of Patent: August 1, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Vivek Kishorechand Arora
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Publication number: 20230207420Abstract: An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Kwang-Soo Kim, Vivek Kishorechand Arora, Woochan Kim
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Publication number: 20230198422Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.Type: ApplicationFiled: February 14, 2023Publication date: June 22, 2023Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
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Patent number: 11601065Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.Type: GrantFiled: August 30, 2021Date of Patent: March 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
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Publication number: 20230060830Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya