Abstract: According to an embodiment, a method for operating a memory system includes receiving data bits at a memory controller for storage in memory, remapping the data bits according to a predetermined scheme as they are transmitted from the controller to memory via a bus, storing the remapped bits in memory, reading the remapped bits from memory via the bus, and inverse remapping the bits to restore their original order as they are transmitted back to the controller. The remapping enhances fault tolerance by spatially separating related bits. The scheme may use techniques like multiplexing, cyclic shifting, or pseudo-random distribution. The remapping can be implemented through hardwired bus connections without adding clock cycles. The method improves resilience to multi-bit errors in wide-word volatile memories used in safety-critical applications, while maintaining compatibility with existing error detection methods.

Abstract: According to an embodiment, a circuit includes a memory cell array storing memory words with data bits, data check bits, and address check bits. An error correction code (ECC) logic circuit includes an address ECC generator circuit generating address check bits, a data ECC generator circuit generating data check bits, an address ECC checker circuit verifying address check bits, and a data ECC checker/correction circuit verifying and correcting data bits using data check bits. A logic circuit arranges the bits within each memory word based on a predetermined arrangement. The address check bits may be scrambled within each word, with at least one as the least or most significant bit. The address ECC may use Single Error Detection Double Error Decoding (SEDDED) and the data ECC may use Single Error Correction Double Error Detection (SECDED). The architecture provides enhanced error detection and correction capabilities for high-integrity memory applications.

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

Abstract: A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of logic 0. The device is further configured to provide an output that has a value of the sum or the difference of the received inputs.

Abstract: A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of logic 0. The device is further configured to provide an output that has a value of the sum or the difference of the received inputs.

Abstract: The configurable logic device provides enhanced flexibility, scalability and area efficient implementation of arithmetic operation on (N?1) bit variables. The device includes a first configurable logic subsystem capable of generating logic OR output in response to functions of N?1 input variables in arithmetic mode, a second configurable logic subsystem capable of generating logic AND output in response to functions of N?1 input variables in arithmetic mode, and a configurable logic block connected at its first input to the output of the first configurable logic subsystem, connected at its second input to the output of the second configurable logic subsystem, connected at its third input to the Nth input variable, and connected at its fourth input to a carry/borrow signal.