Patents by Inventor Vivek Oppula

Vivek Oppula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10674296
    Abstract: An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 2, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Anindya Battacharya, Bhoodev Kumar, John L. Melanson, Vivek Oppula, Anuradha Parsi, Qi Cai
  • Patent number: 10305671
    Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 28, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Bhoodev Kumar, Muraleedharan Ramakrishnan, Vivek Oppula, Thomas Hoff, Willem Zwart
  • Publication number: 20190037327
    Abstract: An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 31, 2019
    Inventors: Anindya Bhattacharya, Bhoodev Kumar, John L. Melanson, Vivek Oppula, Anuradha Parsi, Qi Cai
  • Patent number: 10128828
    Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 13, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Muraleedharan Ramakrishnan, Bhoodev Kumar, Vivek Oppula, Niju Alex Geevarughese
  • Publication number: 20170310315
    Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 26, 2017
    Applicant: Cirrus Logic International Semiconductor, Ltd.
    Inventors: Muraleedharan Ramakrishnan, Bhoodev Kumar, Vivek Oppula, Niju Alex Geevarughese
  • Publication number: 20160344536
    Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Bhoodev Kumar, Muraleedharan Ramakrishnan, Vivek Oppula, Thomas Hoff, Willem Zwart