Patents by Inventor Vivek Raghavan

Vivek Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240106855
    Abstract: This disclosure describes techniques and mechanisms for improving security within SDWAN fabric and utilizing telemetry data from non-enterprise providers to remediate compromised SDWAN site(s) and/or user(s). The techniques may implement an integration of non-enterprise application(s) and API(s) with an enterprise network, thereby enabling the enterprise network to identify compromised endpoint(s), identify user(s), group(s), site(s) that are impacted, and take a corrective action (by the enterprise network and/or the non-enterprise application(s) or API(s)) on the enterprise fabric.
    Type: Application
    Filed: February 7, 2023
    Publication date: March 28, 2024
    Inventors: Balaji Sundararajan, Vivek Agarwal, Vishnuprasad Raghavan, Kannan Kumar, Chandra Balaji Rajaram
  • Patent number: 9576098
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 21, 2017
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Publication number: 20140181762
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: October 29, 2013
    Publication date: June 26, 2014
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Patent number: 8572523
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 29, 2013
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Patent number: 8473876
    Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 25, 2013
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Patent number: 7434188
    Abstract: A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: October 7, 2008
    Assignee: Magma Design Automation, Inc.
    Inventors: Anirudh Devgan, Roderick Metcalfe, Vivek Raghavan, Alfred Wong
  • Publication number: 20080052646
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: July 20, 2007
    Publication date: February 28, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Publication number: 20080052653
    Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: July 20, 2007
    Publication date: February 28, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Patent number: 6286126
    Abstract: Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: September 4, 2001
    Assignee: Avant! Corporation
    Inventors: Vivek Raghavan, Brian A. Zimmerman
  • Patent number: 5896300
    Abstract: A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: April 20, 1999
    Assignee: Avant| Corporation
    Inventors: Vivek Raghavan, Brian Allan Zimmerman
  • Patent number: 5313398
    Abstract: A method and apparatus for simulating a microelectronic circuit includes the steps of storing of a microelectronic circuit or system representation in a computer system and then dividing the circuit or system into portions containing nonlinear elements and linear partitions. The linear partitions are then independently solved for by modelling each linear partition using Asymptotic Waveform Evaluation (AWE) to form multiport admittance macromodels. These macromodels provide admittance and current stencils, which may be functions of time, to a global MNA matrix used by SPICE at each time point to simulate the operation of the entire microelectronic circuit. A linearized transient representation for the nonlinear elements is provided as SPICE admittance and current stencils using conventional techniques. By using AWE techniques to solve the linear partitions separately, significant savings in computation time and improved computational storage efficiency can be achieved.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: May 17, 1994
    Assignee: Carnegie Mellon University
    Inventors: Ronald A. Rohrer, Vivek Raghavan, J. Eric Bracken