Patents by Inventor Vivek Raj

Vivek Raj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220215872
    Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
  • Patent number: 11322200
    Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
  • Patent number: 10764229
    Abstract: Systems, methods, and non-transitory computer-readable media can identify a page within a social networking system. Information associated with at least one of the page or a representative of the page can be acquired. A set of calls to action implementable at the page can be identified. The set of calls to action can be ranked based on the information associated with at least one of the page or the representative of the page.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 1, 2020
    Assignee: Facebook, Inc.
    Inventors: Aaron Gia-Li Chou, Vivek Raj, Zhi Zhong, Dong Guo
  • Publication number: 20170187667
    Abstract: Systems, methods, and non-transitory computer-readable media can identify a page within a social networking system. Information associated with at least one of the page or a representative of the page can be acquired. A set of calls to action implementable at the page can be identified. The set of calls to action can be ranked based on the information associated with at least one of the page or the representative of the page.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Aaron Gia-Li Chou, Vivek Raj, Zhi Zhong, Dong Guo