Patents by Inventor Vivek Rao
Vivek Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190057896Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventors: Robert John STEPHENSON, SCOTT A. KREPS, ROBERT J. MEARS, KALIPATNAM VIVEK RAO
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Publication number: 20190058059Abstract: A semiconductor device may include a semiconductor substrate and first and second spaced apart shallow trench isolation (STI) regions therein, and a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first semiconductor stringer including a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and a gate above the superlattice.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventors: Robert John STEPHENSON, SCOTT A. KREPS, ROBERT J. MEARS, KALIPATNAM VIVEK RAO
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Patent number: 10162610Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises runtime metadata associated with the application, converting, using the metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by creating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: GrantFiled: January 3, 2017Date of Patent: December 25, 2018Assignee: Syntel, Inc.Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Patent number: 10162611Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises at least business rule metadata associated with the application, converting, using the at least business rule metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by creating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: GrantFiled: January 3, 2017Date of Patent: December 25, 2018Assignee: Syntel, Inc.Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Patent number: 10162612Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises runtime metadata associated with the application, converting, using the runtime metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by simulating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: GrantFiled: January 3, 2017Date of Patent: December 25, 2018Assignee: Syntel, Inc.Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Publication number: 20180357055Abstract: A legacy-to-container (L2C) system converts a computer program in a procedural programming language to an object oriented programming language. The L2C system parses the procedural language to identify program variables and also program sub-elements, such as paragraphs in COBOL for example. The L2C system provides a user interface that allows the user to select which paragraphs should be converted into methods wherein the remaining non-selected paragraphs are to be converted into classes. The L2C system is configured to re-architect the procedural language by (i) creating normal object classes corresponding to the identified variables, (ii) creating methods for the user-selected paragraphs; and (iii) creating classes for the remaining non-selected paragraphs.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Abhijit Apte, Vivek Rao, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Rahul Mehra, Amit Pundeer, Abhishek Agarwal, Abhijeet Sheth
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Publication number: 20180358361Abstract: A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.Type: ApplicationFiled: June 13, 2018Publication date: December 13, 2018Inventor: KALIPATNAM VIVEK RAO
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Publication number: 20180358442Abstract: A semiconductor device may include a substrate, at least one memory array comprising a plurality of recessed channel array transistors (RCATs) on the substrate, and periphery circuitry adjacent the at least one memory array and including a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, a superlattice extending between the source and drain regions in the channel region, and a gate over the superlattice and between the source and drain regions. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: June 13, 2018Publication date: December 13, 2018Inventor: KALIPATNAM VIVEK RAO
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Publication number: 20180272076Abstract: Exemplary embodiments provide automatic injection devices in which a shroud is automatically deployed to protectively sheath a needle after an injection is performed. Exemplary embodiments also provide shroud deployment assemblies including a shroud and a syringe carrier that, when cooperatively configured in an automatic injection device, ensure that the shroud is automatically and completely deployed after an injection is performed using the automatic injection device. Exemplary embodiments are also configured to ensure that, once the shroud is deployed to an extended position to sheath the needle, accidental forces applied to the shroud do not succeed in subsequently retracting the shroud to a retracted position in which the needle would become exposed.Type: ApplicationFiled: March 5, 2018Publication date: September 27, 2018Inventors: Vivek Rao, Sherwin Shang, Esra Ozdaryal, Eduard Tsvirko, Edwin Chim, David Post, Vincent DiPalma
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Patent number: 9956353Abstract: Exemplary embodiments provide automatic injection devices in which a shroud is automatically deployed to protectively sheath a needle after an injection is performed. Exemplary embodiments also provide shroud deployment assemblies including a shroud and a syringe carrier that, when cooperatively configured in an automatic injection device, ensure that the shroud is automatically and completely deployed after an injection is performed using the automatic injection device. Exemplary embodiments are also configured to ensure that, once the shroud is deployed to an extended position to sheath the needle, accidental forces applied to the shroud do not succeed in subsequently retracting the shroud to a retracted position in which the needle would become exposed.Type: GrantFiled: March 29, 2012Date of Patent: May 1, 2018Assignee: AbbVie Inc.Inventors: Vivek Rao, Sherwin Shang, Esra Ozdaryal, Eduard Tsvirko, Edwin Chim, David Post, Vincent Dipalma
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Publication number: 20170192777Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises at least business rule metadata associated with the application, converting, using the at least business rule metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by creating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: ApplicationFiled: January 3, 2017Publication date: July 6, 2017Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Publication number: 20170193437Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises runtime metadata associated with the application, converting, using the runtime metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by simulating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: ApplicationFiled: January 3, 2017Publication date: July 6, 2017Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkami, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Publication number: 20170192758Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises runtime metadata associated with the application, converting, using the metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by creating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.Type: ApplicationFiled: January 3, 2017Publication date: July 6, 2017Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
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Publication number: 20160331283Abstract: Systems, devices, and methods are provided for the assembly and subsequent delivery of an in vivo analyte sensor. An applicator with sensor electronics is inserted into a tray containing an assembly that includes a sharp and an analyte sensor. The insertion causes the assembly to couple with the sensor electronics and form a deliverable sensor control device retained within the applicator, which can then be placed in position on a body of a user to monitor that user's analyte levels.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Inventors: Vivek Rao, Tuan Nguyen
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Publication number: 20150214339Abstract: A method to process a semiconductor device includes performing a first ion implant comprising first ions into a thin crystalline semiconductor structure, the first ion dose amorphizing a first region of the thin crystalline semiconductor structure; performing a second ion implant comprising dopant ions of a dopant species into at least the first region of the thin crystalline semiconductor structure; and performing at least one anneal of the semiconductor device after the first implant, wherein after the first and second implant and the at least one anneal, the thin crystalline semiconductor structure forms a mono-crystalline region without defects.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: ANDREW M. WAITE, KALIPATNAM VIVEK RAO
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Publication number: 20140128840Abstract: Exemplary embodiments provide automatic injection devices in which a shroud is automatically deployed to protectively sheath a needle after an injection is performed. Exemplary embodiments also provide shroud deployment assemblies including a shroud and a syringe carrier that, when cooperatively configured in an automatic injection device, ensure that the shroud is automatically and completely deployed after an injection is performed using the automatic injection device. Exemplary embodiments are also configured to ensure that, once the shroud is deployed to an extended position to sheath the needle, accidental forces applied to the shroud do not succeed in subsequently retracting the shroud to a retracted position in which the needle would become exposed.Type: ApplicationFiled: March 29, 2012Publication date: May 8, 2014Applicant: AbbVie Inc.Inventors: Vivek Rao, Sherwin Shang, Esra Ozdaryal, Edward Tsvirko, Edwin Chim, David Post, Vincent DiPalma
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Patent number: 7943361Abstract: The present invention provides mutant Mycobacterium strains harboring a modified tyrosine phosphatase gene (mptpA or mptpB) wherein the mutant Mycobacterium strain is incapable of expressing the active tyrosine phosphatase. The invention provides a method for developing the said mutant strain from either Mycobacterium tuberculosis or Mycobacterium bovis. The mptpA or mptpB gene may be modified by replacing the internal sequences with an antibiotic resistance marker gene, which disrupts the expression of the active gene. The invention further provides a recombinant vector comprising the modified mptpA or mptpB which may be used to develop the mutant strains of mycobacteria. The invention provides a method to assess the role of tyrosine phosphatases MptpA and MptpB in the virulence and pathogenesis of Mycobacterium which can be used as potential targets for developing anti-tubercular drug.Type: GrantFiled: July 9, 2004Date of Patent: May 17, 2011Assignees: Indian Council of Medical Research, University of DelhiInventors: Anil Kumar Tyagi, Ramandeep Singh, Vivek Rao, Vadakkuppattu Devasenapathi Ramanathan, Chinnambedy Nainarappan Paramasivan, Paranji Ramaiyenger Narayanan, Yogendra Singh
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Patent number: 7928425Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.Type: GrantFiled: January 23, 2008Date of Patent: April 19, 2011Assignee: Mears Technologies, Inc.Inventor: Kalipatnam Vivek Rao
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Patent number: 7812339Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.Type: GrantFiled: April 14, 2008Date of Patent: October 12, 2010Assignee: Mears Technologies, Inc.Inventors: Robert J. Mears, Kalipatnam Vivek Rao
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Patent number: 7781827Abstract: A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.Type: GrantFiled: January 23, 2008Date of Patent: August 24, 2010Assignee: Mears Technologies, Inc.Inventor: Kalipatnam Vivek Rao