Patents by Inventor Vivek Shivhare
Vivek Shivhare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260154005Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.Type: ApplicationFiled: January 23, 2026Publication date: June 4, 2026Inventors: John J. Kane, Byron D Harris, Vivek Shivhare
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Publication number: 20260037378Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.Type: ApplicationFiled: October 7, 2025Publication date: February 5, 2026Inventors: Kishore Kumar Muchherla, David Scott Ebsen, Akira Goda, Jonathan S. Parry, Vivek Shivhare, Suresh Rajgopal
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Patent number: 12541320Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.Type: GrantFiled: April 30, 2024Date of Patent: February 3, 2026Assignee: Micron Technology, Inc.Inventors: John J. Kane, Byron D. Harris, Vivek Shivhare
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Patent number: 12498886Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: GrantFiled: August 2, 2024Date of Patent: December 16, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Patent number: 12481463Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: GrantFiled: April 30, 2024Date of Patent: November 25, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Patent number: 12461818Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.Type: GrantFiled: October 9, 2023Date of Patent: November 4, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, David Scott Ebsen, Akira Goda, Jonathan S. Parry, Vivek Shivhare, Suresh Rajgopal
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Publication number: 20250166708Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Yu-Chung Lien, Vivek Shivhare, Vinh Diep, Zhenming Zhou
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Patent number: 12237015Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.Type: GrantFiled: August 15, 2022Date of Patent: February 25, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Yu-Chung Lien, Vivek Shivhare, Vinh Diep, Zhenming Zhou
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Publication number: 20240393980Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Publication number: 20240347128Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Publication number: 20240302999Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: ApplicationFiled: April 30, 2024Publication date: September 12, 2024Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Publication number: 20240302991Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.Type: ApplicationFiled: April 30, 2024Publication date: September 12, 2024Inventors: John J. Kane, Byron D. Harris, Vivek Shivhare
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Patent number: 12079517Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: GrantFiled: July 21, 2022Date of Patent: September 3, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Patent number: 12051479Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: GrantFiled: July 25, 2022Date of Patent: July 30, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Patent number: 12001721Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: GrantFiled: August 5, 2022Date of Patent: June 4, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Patent number: 11995345Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.Type: GrantFiled: July 13, 2022Date of Patent: May 28, 2024Assignee: Micron Technology, Inc.Inventors: John J Kane, Byron D Harris, Vivek Shivhare
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Publication number: 20240118971Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.Type: ApplicationFiled: October 9, 2023Publication date: April 11, 2024Inventors: Kishore Kumar Muchherla, David Scott Ebsen, Akira Goda, Jonathan S. Parry, Vivek Shivhare, Suresh Rajgopal
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Publication number: 20240055052Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.Type: ApplicationFiled: August 15, 2022Publication date: February 15, 2024Inventors: Yu-Chung Lien, Vivek Shivhare, Vinh Diep, Zhenming Zhou
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Publication number: 20240045616Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Publication number: 20240029815Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu