Patents by Inventor Vivek Telang
Vivek Telang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10652008Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: GrantFiled: July 9, 2018Date of Patent: May 12, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Velu Pillai, Vivek Telang
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Publication number: 20180316486Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Applicant: Avago Technologies General IP (Singapore) Ptd. Ltd.Inventors: Velu Pillai, Vivek Telang
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Patent number: 10069620Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: GrantFiled: March 28, 2016Date of Patent: September 4, 2018Assignee: BROADCOM CORPORATIONInventors: Velu Pillai, Vivek Telang
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Publication number: 20160211966Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: ApplicationFiled: March 28, 2016Publication date: July 21, 2016Applicant: BROADCOM CORPORATIONInventors: Velu Pillai, Vivek Telang
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Patent number: 9338040Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: GrantFiled: February 5, 2015Date of Patent: May 10, 2016Assignee: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Patent number: 9304950Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: GrantFiled: September 27, 2012Date of Patent: April 5, 2016Assignee: BROADCOM CORPORATIONInventors: Velu Pillai, Vivek Telang
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Publication number: 20150146766Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: ApplicationFiled: February 5, 2015Publication date: May 28, 2015Applicant: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Patent number: 8964818Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: GrantFiled: January 11, 2013Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventors: Lorenzo Longo, Vivek Telang
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Patent number: 8948237Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.Type: GrantFiled: January 4, 2013Date of Patent: February 3, 2015Assignee: Broadcom CorporationInventors: Namik Kemal Kocaman, Afshin Momtaz, Velu Chellam Pillai, Vivek Telang, Sundararajan Chidambara, Magesh Valliappan
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Patent number: 8913706Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency.Type: GrantFiled: August 20, 2010Date of Patent: December 16, 2014Assignee: Broadcom CorporationInventors: Jun Cao, Afshin Momtaz, Chung-Jue Chen, Kang Xiao, Vivek Telang, Ali Ghiasi
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Publication number: 20140153620Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: ApplicationFiled: January 11, 2013Publication date: June 5, 2014Applicant: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Publication number: 20140075076Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.Type: ApplicationFiled: September 27, 2012Publication date: March 13, 2014Applicant: BROADCOM CORPORATIONInventors: Velu Pillai, Vivek Telang
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Publication number: 20130243072Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: ApplicationFiled: April 26, 2013Publication date: September 19, 2013Applicant: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Patent number: 8442159Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: GrantFiled: September 16, 2010Date of Patent: May 14, 2013Assignee: Broadcom CorporationInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Patent number: 8428111Abstract: Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.Type: GrantFiled: May 1, 2007Date of Patent: April 23, 2013Assignee: Broadcom CorporationInventors: Magesh Valliappan, Howard Baumer, Anthony Brewster, Vivek Telang
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Patent number: 8369453Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.Type: GrantFiled: December 3, 2008Date of Patent: February 5, 2013Assignee: Broadcom CorporationInventors: Namik Kemal Kocaman, Afshin Momtaz, Velu Chellam Pillai, Vivek Telang, Sundararajan Chidambara, Magesh Valliappan
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Patent number: 8130786Abstract: An apparatus is disclosed that includes first transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a first Ethernet communication protocol at a first data rate, second transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a second Ethernet communication protocol at a second data rate; and third transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a third Ethernet communication protocol at a third data rate.Type: GrantFiled: April 30, 2008Date of Patent: March 6, 2012Assignee: Broadcom CorporationInventors: Michael Furlong, Vivek Telang
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Publication number: 20120007640Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency.Type: ApplicationFiled: August 20, 2010Publication date: January 12, 2012Applicant: Broadcom CorporationInventors: Jun CAO, Afshin MOMTAZ, Chung-Jue CHEN, Kang XIAO, Vivek TELANG, Ali GHIASI
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Publication number: 20120002713Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: ApplicationFiled: September 16, 2010Publication date: January 5, 2012Applicant: BROADCOM CORPORATIONInventors: Vivek Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Patent number: 7961781Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.Type: GrantFiled: August 10, 2007Date of Patent: June 14, 2011Assignee: Broadcom CorporationInventors: Vivek Telang, Vasudevan Parthasarathy, Sudeep Bhoja, Hong Chen, Afshin Momtaz, Chung-Jue Chen, Ali Ghiasi, Michael Furlong, Lorenzo Longo