Patents by Inventor Vivek Trivedi
Vivek Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853115Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: September 27, 2022Date of Patent: December 26, 2023Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Patent number: 11487317Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: September 20, 2021Date of Patent: November 1, 2022Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Patent number: 11327913Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.Type: GrantFiled: September 21, 2020Date of Patent: May 10, 2022Assignee: Astera Labs, Inc.Inventors: Casey Morrison, Charan Enugala, Chi Feng, Enrique Musoll, Jitendra Mohan, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Vivek Trivedi
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Patent number: 11258696Abstract: A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.Type: GrantFiled: June 4, 2020Date of Patent: February 22, 2022Assignee: Asiera Labs, Inc.Inventors: Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli, Vikas Khandelwal, Ken (Keqin) Han, Charan Enugala, Vivek Trivedi, Chi Feng
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Patent number: 11150687Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.Type: GrantFiled: July 10, 2020Date of Patent: October 19, 2021Assignee: Astera Labs, Inc.Inventors: Jitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Publication number: 20200155702Abstract: Engineered antibody compounds and conjugates thereof, are provided, said antibody compounds and conjugates thereof are useful as agents for cancer immunotherapy.Type: ApplicationFiled: June 14, 2018Publication date: May 21, 2020Inventors: Michael James Bacica, Yiqing Feng, Donmienne Doen Mun Leung, Matthew D. Linnik, Adam Robert Mezo, James Thomas Parker, Purva Vivek Trivedi, Francisco Alcides Valenzuela, Jianghuai Xu
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Patent number: 10198389Abstract: An information processing system, device and method wherein a base board is configured to couple to both back and midplane systems as well as optical modules for use in a data center rack system. Specifically, a base board adapter is configured to electrically couple to an integrated backplane/midplane electronic interface of the base board and translate the signals to one or more optical interface module connectors such that one or more optical interface modules are able to be coupled to the base board.Type: GrantFiled: July 14, 2014Date of Patent: February 5, 2019Assignee: Cavium, LLCInventors: Amir H. Motamedi, Nikhil Jayakumar, Bhagavathi R. Mula, Vivek Trivedi, Vasant K. Palisetti, Daman Ahluwalia
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Patent number: 9443053Abstract: Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.Type: GrantFiled: December 26, 2013Date of Patent: September 13, 2016Assignee: Cavium, Inc.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Patent number: 9390209Abstract: An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.Type: GrantFiled: December 26, 2013Date of Patent: July 12, 2016Assignee: CAVIUM, INC.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Patent number: 9305129Abstract: Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.Type: GrantFiled: December 26, 2013Date of Patent: April 5, 2016Assignee: Cavium, Inc.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Publication number: 20160014885Abstract: An information processing system including a support structure supporting a plurality of blade boards configured to detachably couple to an electronic interface of the structure. The blade boards each include a printed circuit board having a front board edge, one or more optical interface modules positioned on the front edge of the circuit board and a processing chip coupled to the circuit board and having a plurality of pin outs that are each electrically coupled to at least one of the optical interface modules via one or more traces on the circuit board. Further, the sides of the processing chip are non-parallel with the front board edge of the printed circuit board. As a result, the board is able to simultaneously reduce trace length and increase cooling efficiency of the system.Type: ApplicationFiled: July 14, 2014Publication date: January 14, 2016Inventors: Amir H. Motamedi, Nikhil Jayakumar, Bhagavathi R. Mula, Vivek Trivedi, Vasant K. Palisetti, Daman Ahluwalia
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Publication number: 20160012006Abstract: An information processing system, device and method wherein a base board is configured to couple to both back and midplane systems as well as optical modules for use in a data center rack system. Specifically, a base board adapter is configured to electrically couple to an integrated backplane/midplane electronic interface of the base board and translate the signals to one or more optical interface module connectors such that one or more optical interface modules are able to be coupled to the base board.Type: ApplicationFiled: July 14, 2014Publication date: January 14, 2016Inventors: Amir H. Motamedi, Nikhil Jayakumar, Bhagavathi R. Mula, Vivek Trivedi, Vasant K. Palisetti, Daman Ahluwalia
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Patent number: 9098664Abstract: A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels.Type: GrantFiled: February 28, 2014Date of Patent: August 4, 2015Assignee: Juniper Networks, Inc.Inventors: Vivek Trivedi, Khalil Siddiqui
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Publication number: 20150186589Abstract: Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: XPLIANT, Inc.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Publication number: 20150186583Abstract: Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: XPLIANT, Inc.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Publication number: 20150186560Abstract: An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: XPLIANT, Inc.Inventors: Nikhil Jayakumar, Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi
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Publication number: 20140181778Abstract: A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels.Type: ApplicationFiled: February 28, 2014Publication date: June 26, 2014Applicant: JUNIPER NETWORKS, INC.Inventors: Vivek Trivedi, Khalil Siddiqui
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Patent number: 8683416Abstract: A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a channel implementation area, corresponding to the substrate, for each of a plurality of signal channels, based on the channel priority assigned to the signal channel and based on the block implementation areas. The device may generate an integrated circuit design comprising the channel implementation area allocated for each of the plurality of signal channels.Type: GrantFiled: July 28, 2011Date of Patent: March 25, 2014Assignee: Juniper Networks, Inc.Inventors: Vivek Trivedi, Khalil Siddiqui
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Patent number: 7299433Abstract: An apparatus and a system, as well as a method and article, may operate to include receiving initial static timing environment data associated with a circuit at a graphical user interface, and generating a data file including a plural of all possible sources of a generated clock included in the circuit.Type: GrantFiled: June 9, 2003Date of Patent: November 20, 2007Assignee: Intel CorporationInventors: Manuel S. Clement, Vivek Trivedi, Sadiq Mohiuddin
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Publication number: 20040250224Abstract: An apparatus and a system, as well as a method and article, may operate to include receiving initial static timing environment data associated with a circuit at a graphical user interface, and generating a data file including a plurality of all Possible sources of a generated clock included in a circuit.Type: ApplicationFiled: June 9, 2003Publication date: December 9, 2004Applicant: Intel CorporationInventors: Manuel S. Clement, Vivek Trivedi, Sadiq Mohiuddin