Patents by Inventor Vivek Venkata Kalluru
Vivek Venkata Kalluru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11763858Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.Type: GrantFiled: August 17, 2022Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Vivek Venkata Kalluru, Michele Piccardi
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Publication number: 20230057289Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.Type: ApplicationFiled: February 10, 2022Publication date: February 23, 2023Inventors: Vivek Venkata Kalluru, Michele Piccardi, Taehyun Kim, Theodore T. Pekny
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Publication number: 20220392498Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.Type: ApplicationFiled: August 17, 2022Publication date: December 8, 2022Inventors: Vivek Venkata Kalluru, Michele Piccardi
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Patent number: 11443778Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including: detecting that the charge pump has entered a recovery period; causing the oscillator to output, to the charge pump during a first time period of the recovery period, a first clock signal comprising a lower frequency than output during a time period preceding the recovery period; detecting that a voltage level from the level detector satisfies a trip point criterion; and causing the oscillator to output, to the charge pump during a second time period of the recovery period and responsive to the detecting, a second clock signal comprising a higher frequency than output during the time period preceding the recovery period.Type: GrantFiled: April 7, 2021Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Vivek Venkata Kalluru, Michele Piccardi
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Patent number: 11056197Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.Type: GrantFiled: July 31, 2020Date of Patent: July 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Min, Vivek Venkata Kalluru, Tae-hong Kwon, Ki-won Kim, Sung-whan Seo, Bilal Ahmad Janjua
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Patent number: 10902926Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.Type: GrantFiled: November 6, 2019Date of Patent: January 26, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sun Min, Vivek Venkata Kalluru, Tae-hong Kwon, Ki-won Kim, Sung-whan Seo, Bilal Ahmad Janjua
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Patent number: 10867673Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.Type: GrantFiled: August 17, 2019Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Bilal Ahmad Janjua, Vivek Venkata Kalluru, June-Hong Park, Jungyu Lee, Ji-Hoon Lim
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Publication number: 20200365215Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Young-sun MIN, Vivek Venkata KALLURU, Tae-hong KWON, Ki-won KIM, Sung-whan SEO, Bilal Ahmad JANJUA
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Patent number: 10707751Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.Type: GrantFiled: August 24, 2019Date of Patent: July 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Bilal Ahmad Janjua, Sungwhan Seo, Vivek Venkata Kalluru
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Publication number: 20200152277Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.Type: ApplicationFiled: November 6, 2019Publication date: May 14, 2020Inventors: Young-sun MIN, Vivek Venkata KALLURU, Tae-hong KWON, Ki-won KIM, Sung-whan SEO, Bilal Ahmad JANJUA
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Publication number: 20200152265Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.Type: ApplicationFiled: August 17, 2019Publication date: May 14, 2020Inventors: BILAL AHMAD JANJUA, VIVEK VENKATA KALLURU, JUNE-HONG PARK, JUNGYU LEE, JI-HOON LIM
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Publication number: 20200144910Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.Type: ApplicationFiled: August 24, 2019Publication date: May 7, 2020Inventors: BILAL AHMAD JANJUA, SUNGWHAN SEO, VIVEK VENKATA KALLURU
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Patent number: 10613571Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.Type: GrantFiled: January 24, 2019Date of Patent: April 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Surojit Sarkar, Vivek Venkata Kalluru, Youngsun Min, Ji-Hoon Lim
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Publication number: 20200105345Abstract: A leakage current compensation device includes a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines, a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current, and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.Type: ApplicationFiled: April 15, 2019Publication date: April 2, 2020Inventors: JONG MIN BAEK, VIVEK VENKATA KALLURU, JONG RYUL KIM, BILAL AHMAD JANJUA
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Publication number: 20190377377Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.Type: ApplicationFiled: January 24, 2019Publication date: December 12, 2019Inventors: Surojit Sarkar, Vivek Venkata Kalluru, Youngsun Min, Ji-Hoon Lim
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Patent number: 9685238Abstract: A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage.Type: GrantFiled: April 19, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Venkataramana Gangasani, Sung-Whan Seo, Hi-Choon Lee, Vivek Venkata Kalluru
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Publication number: 20170011806Abstract: A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage.Type: ApplicationFiled: April 19, 2016Publication date: January 12, 2017Inventors: VENKATARAMANA GANGASANI, SUNG-WHAN SEO, HI-CHOON LEE, VIVEK VENKATA KALLURU
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Patent number: 9369115Abstract: A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.Type: GrantFiled: March 4, 2015Date of Patent: June 14, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Vivek Venkata Kalluru, Youngsun Min, Hichoon Lee
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Publication number: 20150288353Abstract: A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.Type: ApplicationFiled: March 4, 2015Publication date: October 8, 2015Inventors: VIVEK VENKATA KALLURU, YOUNGSUN MIN, HICHOON LEE
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Patent number: 8710909Abstract: Techniques are presented to reduce reversion leakage in charge pump circuits. The exemplary circuit is a charge pump of the voltage doubler type, where the output of each leg is supplied through a corresponding output transistor. An auxiliary charge pump is used to supply the gates of the output transistors in order to cancel the threshold voltage of these output transistors. To reduce reverse leakage back through the output transistors, in each leg of the charge pump a switch is connected between the gate of the output transistor and the output level of the leg so the these levels can be shorted when that particular is not supplying the pump's output.Type: GrantFiled: September 14, 2012Date of Patent: April 29, 2014Assignee: SanDisk Technologies Inc.Inventors: Vivek Venkata Kalluru, Sridhar Yadala, Sriganesh Chandrasekaran