Abstract: Embedded memory structures and methods where an array of bitcells is interconnected by a plurality of bitlines and wordlines, each bitcell comprising a transistor connected to one of the wordlines and one of the bitlines. A TRNG circuit, peripheral to the array of bitcells, sets transistors connected to the one or more of the bitlines to an off state, determines a time interval between different crossing thresholds in a voltage discharge in the bitlines, and digitizes the time interval into bits of an TRNG output. A PUF circuit. peripheral to the array of bitcells, sets a pair of transistors connected to the pair of bitlines and the same wordline to an underdriven state, determines respective times of the transistors of the pair crossing a threshold in a voltage discharge in the pair of bitlines, and digitizes a time difference into an n-bit PUF output.