Abstract: An integrated circuit having an integrated circuit die and at least one height-sensing pad disposed on a top surface of the integrated circuit die and electrically isolated from the die circuitry. At least one bond pad is disposed on a top surface of the integrated circuit die and electrically connected to the die circuitry. The at least one bond pad is configured for wire-bonding to a lead of a leadframe utilizing a height coordinate of the at least one height-sensing pad.

Abstract: Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a top surface of an integrated circuit die. The height-sensing pad is electrically isolated from the die circuitry and the bond pad is electrically connected to the die circuitry. A bonding tool is lowered to the height-sensing pad, and a height coordinate of the height-sensing pad is then determined. Finally, the bond pad is wire-bonded to a leadframe utilizing the height coordinate of the height-sensing pad.

Abstract: The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

Abstract: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 ?m in height and advantageously within 100 ?m of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

Abstract: An integrated circuit die includes a substrate having a front surface and a back surface, wherein the substrate front surface has electrical circuits formed thereon, and the substrate back surface has a plurality of metal layers formed thereon. The plurality of metal layers comprises at least one layer having a thickness of greater than about ten micrometers. The outermost metal layer may be mechanically and thermally bonded to a package using a die attach layer comprising a thermally conductive reflowable material. The invention advantageously facilitates the dissipation of heat from the integrated circuit die.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature and a conductive via located within the dielectric layer and contacting the conductive feature. The semiconductor device, among other elements, may further include a dummy conductive via located proximate the conductive via and contacting the conductive feature. One of the intents of the dummy conductive via is to attempt to trap vacancies associated with the conductive feature or the conductive via.

Abstract: Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on exposed dielectric films or other portions of the die. For example, one aspect of the invention is a method of detecting damage to a dielectric film used in fabricating a die of an integrated circuit. A particle suspension solution is applied to the die and damaged regions of the dielectric film are identified as areas having an accumulation of particles of the particle suspension solution.

Abstract: Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on exposed dielectric films or other portions of the die. For example, one aspect of the invention is a method of detecting damage to a dielectric film used in fabricating a die of an integrated circuit. A particle suspension solution is applied to the die and damaged regions of the dielectric film are identified as areas having an accumulation of particles of the particle suspension solution.

Abstract: Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a top surface of an integrated circuit die. The height-sensing pad is electrically isolated from the die circuitry and the bond pad is electrically connected to the die circuitry. A bonding tool is lowered to the height-sensing pad, and a height coordinate of the height-sensing pad is then determined. Finally, the bond pad is wire-bonded to a leadframe utilizing the height coordinate of the height-sensing pad.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer.

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer.