Patents by Inventor Vivian Wanda Ryan

Vivian Wanda Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6833557
    Abstract: An apparatus and process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one of more different metallization layers within the integrated circuit. The conductive region is couple to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: December 21, 2004
    Assignee: Agere Systems Inc.
    Inventors: Vivian Wanda Ryan, Thomas Herbert Shilling
  • Patent number: 6620720
    Abstract: The specification describes a process for forming a barrier layer on copper metallization in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the barrier layer for wire bond interconnections and copper bond pads are formed on the barrier layer for solder bump interconnections.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 16, 2003
    Assignee: Agere Systems INC
    Inventors: Ralph Salvatore Moyer, Vivian Wanda Ryan
  • Patent number: 6621280
    Abstract: A process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one or more different metallization layers within the integrated circuit. The conductive region is coupled to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: September 16, 2003
    Assignee: Agere Systems Inc.
    Inventors: Vivian Wanda Ryan, Thomas Herbert Shilling
  • Patent number: 6004827
    Abstract: A variety of test structures may be fabricated with aluminum runners and overlying dielectrics. The dielectrics are removed and bumps are observed upon the aluminum runners. Unevenness in the bump distribution is a predictor of long term reliability problems. A test structure may be utilized to design integrated mass production fabrication processes.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: December 21, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Vivian Wanda Ryan