Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.

Abstract: A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.

Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code “grabbing”. The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code “grabbing”. The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code "grabbing". The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.