Patents by Inventor Vjekoslav Svilan
Vjekoslav Svilan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210191490Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Inventors: Phani Kumar KANDULA, Eric J. DEHAEMER, Dorit SHAPIRA, Ramkumar NAGAPPAN, Vivek GARG, Fuat KECELI, Mani PRAKASH, David C. HOLCOMB, Horthense D. TAMDEM, Olivier FRANZA, Vjekoslav SVILAN
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Patent number: 10955885Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.Type: GrantFiled: March 11, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
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Patent number: 10802567Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: GrantFiled: December 21, 2017Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Patent number: 10725524Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.Type: GrantFiled: March 2, 2016Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Jawad Nasrullah, Kelvin Kwan, David Roger Ditzel, Vjekoslav Svilan
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Publication number: 20190204886Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Applicant: Intel CorporationInventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
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Patent number: 10228738Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.Type: GrantFiled: December 27, 2011Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
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Patent number: 10108454Abstract: In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.Type: GrantFiled: March 21, 2014Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Vjekoslav Svilan, David N. Mackintosh
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Publication number: 20180129265Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2017Publication date: May 10, 2018Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Publication number: 20180129266Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2017Publication date: May 10, 2018Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Publication number: 20170371397Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: ApplicationFiled: July 12, 2017Publication date: December 28, 2017Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Patent number: 9772674Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: GrantFiled: December 7, 2015Date of Patent: September 26, 2017Assignee: Intel CorporationInventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Patent number: 9594412Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2012Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Vjekoslav Svilan, Michael Zelikson, Kelvin Kwan, Naveen Neelakantam, Norbert Unger
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Publication number: 20160179175Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.Type: ApplicationFiled: March 2, 2016Publication date: June 23, 2016Inventors: Jawad Nasrullah, Kelvin Kwan, David Roger Ditzel, Vjekoslav Svilan
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Publication number: 20160085287Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: ApplicationFiled: December 7, 2015Publication date: March 24, 2016Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Patent number: 9280190Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.Type: GrantFiled: December 21, 2011Date of Patent: March 8, 2016Assignee: Intel CorporationInventors: Jawad Nasrullah, Kelvin Kwan, David Roger Ditzel, Vjekoslav Svilan
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Patent number: 9229524Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: GrantFiled: June 27, 2012Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Publication number: 20150268997Abstract: In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Inventors: Vjekoslav Svilan, David N. Mackintosh
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Publication number: 20150149794Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.Type: ApplicationFiled: December 27, 2011Publication date: May 28, 2015Applicant: Intel CorporationInventors: Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
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Publication number: 20140006817Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
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Publication number: 20130275782Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2012Publication date: October 17, 2013Inventors: Vjekoslav Svilan, Michael Zelikson, Kelvin Kwan, Naveen Neelakantam, Norbert Unger