Abstract: A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

Abstract: A gate driver to control a high-power switching device is disclosed. The gate driver includes a multifunction pin that allows the gate driver to be controlled by a multifunction signal to perform a number of different functions. For example, a level of the multifunction signal at the multifunction pin can enable/disable the output of the gate driver. In another example, a level of the multifunction signal that is held for a period while the gate driver is in a fault state can reset the state of the gate driver. In another example, pulsing the multifunction signal a number of times can activate a test of the fault detection capabilities of the gate driver. Utilizing one pin for this control, simplifies circuit complexity for communication between a controller and the gate driver, thereby reducing cost and increasing reliability.

Abstract: A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

Abstract: A power system including a gate driver configured with test circuitry to detect faults is disclosed. The power system may be configured to test the fault detection circuitry in order to confirm its ability to detect faults. Various methods and circuit implementations are disclosed to determine the ability of the system to detect faults. The testing may include different configurations and protocols in order to make conclusions about which components are likely responsible for a failure. These components may include components included in the gate driver or externally coupled to the gate driver. The disclose approach does not significantly add complexity because a test input to initiate a test may be communicated from a low voltage side to a high voltage side over a shared communication channel.