Patents by Inventor Vladimir A. Stoica

Vladimir A. Stoica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9722113
    Abstract: A multilayer stack including a substrate, an active layer, and a tetradymite buffer layer positioned between the substrate and the active layer is disclosed. A method for fabricating a multilayer stack including a substrate, a tetradymite buffer layer and an active layer is also disclosed. Use of such stacks may be in photovoltaics, solar cells, light emitting diodes, and night vision arrays, among other applications.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 1, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Vladimir A. Stoica, Lynn Endicott, Roy Clarke, Ctirad Uher
  • Publication number: 20160027938
    Abstract: A multilayer stack including a substrate, an active layer, and a tetradymite buffer layer positioned between the substrate and the active layer is disclosed. A method for fabricating a multilayer stack including a substrate, a tetradymite buffer layer and an active layer is also disclosed. Use of such stacks may be in photovoltaics, solar cells, light emitting diodes, and night vision arrays, among other applications.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 28, 2016
    Inventors: Vladimir A. STOICA, Lynn ENDICOTT, Roy CLARKE, Ctirad UHER
  • Patent number: 8264693
    Abstract: A method of measuring at least one property including a magnetic property of target material is provided. A pump pulse train having one or more pump pulses is generated. The target material is irradiated with at least a portion of the one or more pump pulses so as to cause transient perturbation in the target material. At least one probe pulse train is generated having one or more probe pulses. The target material is irradiated with at least a portion of the one or more probe pulses to obtain one or more reflected probe pulses which are modulated based on the transient perturbation. A time interval between a time at which the target material is irradiated by each of the pump pulses and a time at which the target material is irradiated by each of its corresponding probe pulses is controlled. Each modulated probe pulse is detected.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: September 11, 2012
    Assignee: The Regents of The University of Michigan
    Inventors: Vladimir A. Stoica, Roy Clarke
  • Publication number: 20090212769
    Abstract: A method of measuring at least one property including a magnetic property of target material is provided. The method includes the step of generating a pump pulse train having one or more pump pulses at a repetition rate along a first propagation path, each pump pulse having a pulse energy density, a laser wavelength within a range of laser wavelengths, and a pulse duration The method further includes the step of irradiating the target material with at least a portion of the one or more pump pulses focused into at least one spot having a spot shape and size so as to cause transient perturbation in the target material. The method still further includes the step of generating at least one probe pulse train having one or more probe pulses at a repetition rate along a second propagation path, each probe pulse having a pulse energy density, a laser wavelength within a range of laser wavelengths, and a pulse duration.
    Type: Application
    Filed: December 8, 2008
    Publication date: August 27, 2009
    Inventors: Vladimir A. Stoica, Roy Clarke
  • Patent number: 7215557
    Abstract: An assembly that includes two or more microelectronic modules in a self-sustaining structure that is adapted to be installed in a housing. The microelectronic modules are affixed to supports that are attached to ribs and arranged in parallel-spaced relationship. When the assembly is received in a housing, the ribs engage the inner wall of the housing to securely position the assembly. Also, the ribs space the microelectronic modules apart from the housing to facilitate coolant gas flow through the housing and thereby improve thermal dissipation during operation.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Vladimir Stoica
  • Patent number: 7180736
    Abstract: A microelectronic package comprises microelectronic assemblies and a housing having a cylindrical outer wall. The microelectronic assemblies include electronic components mounted on a substrate and are affixed to support surfaces of the inner wall of the housing. The housing is preferably formed of semi-cylindrical sections that are joined along axial edges. The housing includes one or more axial channels interposed between the outer wall and the inner wall for conveying coolant gas. In this manner, the housing provides more uniform thermal dissipati9on of heat generated by the microelectronic assemblies during operation, despite variations in the thickness between the cylindrical outer wall and the support surfaces, which are preferably planar.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: February 20, 2007
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Vladimir Stoica
  • Publication number: 20060176677
    Abstract: An assembly that includes two or more microelectronic modules in a self-sustaining structure that is adapted to be installed in a housing. The microelectronic modules are affixed to supports that are attached to ribs and arranged in parallel-spaced relationship. When the assembly is received in a housing, the ribs engage the inner wall of the housing to securely position the assembly. Also, the ribs space the microelectronic modules apart from the housing to facilitate coolant gas flow through the housing and thereby improve thermal dissipation during operation.
    Type: Application
    Filed: August 27, 2003
    Publication date: August 10, 2006
    Inventors: Andrew Glovatsky, Vladimir Stoica
  • Publication number: 20050007736
    Abstract: A microelectronic package comprises microelectronic assemblies and a housing having a cylindrical outer wall. The microelectronic assemblies include electronic components mounted on a substrate and are affixed to support surfaces of the inner wall of the housing. The housing is preferably formed of semi-cylindrical sections that are joined along axial edges. The housing includes one or more axial channels interposed between the outer wall and the inner wall for conveying coolant gas. In this manner, the housing provides more uniform thermal dissipation of heat generated by the microelectronic assemblies during operation, despite variations in the thickness between the cylindrical outer wall and the support surfaces, which are preferably planar.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 13, 2005
    Inventors: Andrew Glovatsky, Vladimir Stoica
  • Patent number: 6838623
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Lawrence Kneisel, Mohan Paruchuri, Vivek Jairazboy, Vladimir Stoica
  • Patent number: 6778389
    Abstract: A microelectronic package comprises a tubular housing and a microelectronic assembly affixed to a support that is received in the housing. The support may be a cage-like structure that comprises axial ribs to which the microelectronic assembly is attached. Alternately, the support may comprise a solid surface for affixing a flexible substrate. The microelectronic assembly is arranged with a major surface facing and spaced apart from the inner wall of the housing. Thus, the microelectronic assembly is proximate to the wall to provide an optimum volume for packaging other components. Movement, the spacing between the microelectronic assembly and the tubular housing facilitates coolant gas flow during use to enhance thermal dissipation.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 17, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Vladimir Stoica
  • Publication number: 20030102152
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Application
    Filed: November 20, 2002
    Publication date: June 5, 2003
    Inventors: Lawrence Leroy Kneisel, Mohan Paruchuri, Vivek Jairazbhoy, Vladimir Stoica
  • Patent number: 6495053
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 17, 2002
    Assignee: Visteon Global Tech, Inc.
    Inventors: Lawrence Leroy Kneisel, Mohan R. Paruchuri, Vivek Amir Jalrazbhoy, Vladimir Stoica
  • Patent number: 6454878
    Abstract: A method for forming sets of tri-metal material involving the use of cladding mills. When multiple sets of tri-metal material are formed, the outside surfaces of each set is prepared by oxidation to prevent each set from adhering to the set above or below. An alternative to oxidation is to provide a removable layer on the outside surface of the tri-metal material. Alternatively bonding materials may be used on the intermediate surfaces; such bonding materials can be selected from a group consisting of tin, nickel, titanium, chromium, silver and zinc.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: September 24, 2002
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Achyuta Achari, Brenda Joyce Nation, Jay D Baker, Lakhi Nandlal Goenka, Mohan R. Paruchuri, Vladimir Stoica
  • Patent number: 6391211
    Abstract: A method for making multi-layer electronic circuit board including a pre-circuit assembly 12 and a ground layer 14 which are automatically aligned and bonded together by use of solder material or deposits 26, 28.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: May 21, 2002
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Robert Joseph Gordon, Vivek Amir Jairazbhoy, Vladimir Stoica