Patents by Inventor Vladimir Aleksandar Zivkovic

Vladimir Aleksandar Zivkovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing circuit and method
    Patent number: 8566656
    Abstract: A test interface circuit operates with different types of core circuits. As consistent with various embodiments, the test interface circuit includes a test input register (TIR) configured to select an operating mode and a plurality of test point registers (TPRs). Each TPR is configured to control signals passed from the input port to a mixed-signal core circuit, responsive to the received test input signals and the operating mode selected by a TIR. In a static mode, each TPR provides serial access to digital inputs and outputs of a mixed-signal core circuit. In a bypass mode, each TPR bypasses TPR slices to preserve test time in response to the TPR being chained to other ones of the TPRs during integration of at least two mixed-signal cores.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: October 22, 2013
    Assignee: NXP B.V.
    Inventors: Vladimir Aleksandar Zivkovic, Frank van der Heijden, Geert Seuren, Steven Oostdijk, Mario Konijnenburg
  • Testing Circuit and Method
    Publication number: 20110148445
    Abstract: A test interface circuit operates with different types of core circuits. As consistent with various embodiments, the test interface circuit includes a test input register (TIR) configured to select an operating mode and a plurality of test point registers (TPRs). Each TPR is configured to control signals passed from the input port to a mixed-signal core circuit, responsive to the received test input signals and the operating mode selected by a TIR. In a static mode, each TPR provides serial access to digital inputs and outputs of a mixed-signal core circuit. In a bypass mode, each TPR bypasses TPR slices to preserve test time in response to the TPR being chained to other ones of the TPRs during integration of at least two mixed-signal cores.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Vladimir Aleksandar Zivkovic, Frank van der Heijden, Geert Seuren, Steven Oostdijk, Mario Konijnenburg