Patents by Inventor Vladimir Bliznetsov
Vladimir Bliznetsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210104659Abstract: Various embodiments may provide a memory cell including a magnetic pinned layer with a substantially fixed magnetization direction, a crystalline spacer layer in contact with the magnetic pinned layer, and a magnetic storage layer. The magnetic storage layer may include an amorphous interface sub-layer in contact with the crystalline spacer layer, the amorphous interface sub-layer including a first alloy of iron (Fe) and at least one element. The amorphous storage layer may also include an amorphous enhancement sub-layer in contact with the amorphous interface sub-layer, the amorphous enhancement sub-layer including a second alloy of iron (Fe) and at least one element. The memory cell may additionally include a cap layer in contact with the amorphous enhancement sub-layer. A concentration of the at least one further element comprised in the first alloy and a concentration of the at least one further element comprised in the second alloy may be different.Type: ApplicationFiled: January 19, 2017Publication date: April 8, 2021Inventors: Hideaki Fukuzawa, Jun Yu, Michael Han, Xinpeng Wang, Vladimir Bliznetsov
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Publication number: 20160308013Abstract: A semiconductor device production method includes preparing a first structure having a first planar semiconductor layer, and a first columnar semiconductor layer on the first planar semiconductor layer. A first high concentration semiconductor layer is formed in a lower region of the first columnar semiconductor layer and in a region of the first planar semiconductor layer below the first columnar semiconductor layer. An insulating layer, a metal film, and a semiconductor film are sequentially formed on the first structure, and the semiconductor film, the metal film, and the insulating layer are sequentially etched with each leaving a sidewall shape on the sidewall on the first columnar semiconductor layer following etching. Another semiconductor film is then formed on the sidewall shape after etching the insulating film.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Publication number: 20150357428Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Patent number: 9153697Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: GrantFiled: May 26, 2011Date of Patent: October 6, 2015Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8609494Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 16, 2013Date of Patent: December 17, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130252413Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: Unisantis Eletronics Singapore Pte.Ltd.Inventors: Fujio MASUOKA, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8486785Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 23, 2011Date of Patent: July 16, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110303985Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 23, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110303973Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 7248773Abstract: Formation, through etching, of structures whose minimum width is less than can be achieved by optical means alone has been achieved by inserting a layer of sandwiching material between the photoresist (or hard mask if used) and the structure. By adjustment of the relative etch rates of this layer and the structure, a uniform lateral width reduction and surface smoothing of the structure is achieved.Type: GrantFiled: December 4, 2006Date of Patent: July 24, 2007Assignee: Agency For Science, Technology, and ResearchInventors: Chang Kuo Chang, Chi Fo Tsang, My The Doan, Ramana Murthy Badam, Vladimir Bliznetsov
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Publication number: 20070090089Abstract: Formation, through etching, of structures whose minimum width is less than can be achieved by optical means alone has been achieved by inserting a layer of sandwiching material between the photoresist (or hard mask if used) and the structure. By adjustment of the relative etch rates of this layer and the structure, a uniform lateral width reduction and surface smoothing of the structure is achieved.Type: ApplicationFiled: December 4, 2006Publication date: April 26, 2007Inventors: Chang Chang, Chi Tsang, My Doan, Ramana Badam, Vladimir Bliznetsov
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Patent number: 7162133Abstract: Formation, through etching, of structures whose minimum width is less than can be achieved by optical means alone has been achieved by inserting a layer of sandwiching material between the photoresist (or hard mask if used) and the structure. By adjustment of the relative etch rates of this layer and the structure, a uniform lateral width reduction and surface smoothing of the structure is achieved.Type: GrantFiled: August 20, 2004Date of Patent: January 9, 2007Assignee: Agency for Science Technology and ResearchInventors: Chang Kuo Chang, Chi Fo Tsang, My The Doan, Ramana Murthy Badam, Vladimir Bliznetsov
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Publication number: 20060037364Abstract: Formation, through etching, of structures whose minimum width is less than can be achieved by optical means alone has been achieved by inserting a layer of sandwiching material between the photoresist (or hard mask if used) and the structure. By adjustment of the relative etch rates of this layer and the structure, a uniform lateral width reduction and surface smoothing of the structure is achieved.Type: ApplicationFiled: August 20, 2004Publication date: February 23, 2006Inventors: Chang Chang, Chi Tsang, My Doan, Ramana Badam, Vladimir Bliznetsov