Abstract: The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

Abstract: The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

Abstract: Optimization of decoupling design selection for electronic designs is described. Initially an electronic design, such as, a printed circuit board, having a power delivery network with a given impedance value is identified. A target impedance value for the power delivery network is also identified. Subsequently, a decoupling impedance value, that, if added to the impedance of the power delivery network would transform the given impedance value into the target impedance value, is derived. In many implementations, the power delivery network may have a number of ports. Accordingly, a decoupling impedance value may be derived for each port. A selection of decoupling devices, each having a given impedance value, are also identified. Subsequently, a system of equations is formed that relates the decoupling devices and their associated impedance values to the decoupling impedance values.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circuit design flow to analyze signal integrity or other electrical behavior. For example, in one exemplary embodiment, a sequence of code words to be input on a circuit channel is determined in a nonrandom manner. In this embodiment, the sequence of code words complies with a transmission code (for example, the 8b10b transmission code) and is designed to cause the output voltage of the channel to be reduced during a time period in which the channel outputs a logic high value.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways that exhibit duty-cycle distortion (e.g., clock-related duty-cycle distortion or data-dependent duty-cycle distortion). In one exemplary embodiment, a period of an input signal is divided into two or more subintervals, each subinterval having a duration that is different from other subintervals. Pulse representations are generated for each of the subintervals, the pulse representations representing pulse durations corresponding to the respective durations of each of the subintervals. Inverted sampled pulse responses are generated to the pulse representations. Samples from two or more of the inverted sampled pulse responses are combined to create one or more combined inverted sampled pulse responses.