Abstract: A method and apparatus for configuring multiple displays includes determining, in connection with an image or portion thereof to be displayed on the multiple displays at the same time, whether received display preferences can be fulfilled in observance of: configuration properties of the multiple displays and configuration properties of a computing system, such as the capabilities of display controllers. The method and apparatus also determine whether a current configuration of the multiple displays to the computing system can be reconfigured such that the display preferences of the multiple displays can be fulfilled at the same time while maintaining effective configuration of a current configuration when the display preferences cannot be fulfilled, and display the images of a portion thereof on the multiple displays at the same time.

Abstract: The present application discloses a method for communicating between at least two different levels of software components. The method includes establishing a command set common to the at least two different levels of software components. Additionally, the method includes providing a command decoder operable by both of the at least two levels of software components, the command decoder configured to decode the command set. By providing a common command set between different levels of software components, such as a software driver and a BIOS, where the commands within the command table are interpreted and executed by an identical command decoder that interprets and executes the same command tables, this ensures that the same features or functions are implemented or executed in the same way across different levels of the software components. Accordingly, redundant implementation of the same functions by different software components is eliminated.

Abstract: A method and apparatus for configuring multiple displays associated with a computing system begins when display preferences regarding at least one of the multiple displays are received. The display preferences indicate desired selections of which images are to be displayed on which displays and may be based on user selections or application selections. Having received the display preferences, a coupling controller within a video graphics processing circuit determines whether the display preferences can be fulfilled in observance of configuration properties. The configuration properties include limitations of the displays (e.g., refresh rate, resolution) and the computing system (e.g., display controller capabilities) and/or rules of the computing system (e.g., at least one screen must be actively coupled at all times). If the display preferences can be fulfilled, the coupling controller causes display controllers to be operably coupled to displays.

Abstract: A method and apparatus for configuring multiple displays associated with a computing system begins when display preferences regarding at least one of the multiple displays are received. The display preferences indicate desired selections of which images are to be displayed on which displays and may be based on user selections or application selections. Having received the display preferences, a coupling controller within a video graphics processing circuit determines whether the display preferences can be fulfilled in observance of configuration properties. The configuration properties include limitations of the displays (e.g., refresh rate, resolution) and the computing system (e.g., display controller capabilities) and/or rules of the computing system (e.g., at least one screen must be actively coupled at all times). If the display preferences can be fulfilled, the coupling controller causes display controllers to be operably coupled to displays.

Abstract: The computer system operates a plurality of display devices 100 and 102. Such a computer system has at least a first video adapter 203 with a first video BIOS and a second video adapter 207 with a second video BIOS. A system BIOS identifies one of the first and second video adapters 203, 207 as a primary video adapter and the other of the first and second video adapters 203, 207 as a secondary video adapter. During POST, the system BIOS stores the first video BIOS in a first memory area 210 in a system memory 212 of the computer. The system BIOS or Video BIOS then copies the first video BIOS to a second memory area 214 in the system memory 212 when the first video adapter 203 is the secondary video adapter. The system BIOS POSTs the second video BIOS when the second video adapter 207 is the primary video adapter, and stores the second video BIOS in the first memory area 210. This then causes the first video BIOS in the first memory area 210 to be overwritten by the second video BIOS.

Abstract: The invention synchronizes and mixes multiple streams at different sampling rates by selectively accessing portions of the received streams in a sequence that allows for independent input and output frame rates. The sequence that is used to access the received streams is irregular with regard to the output frames, and formulated such that the input and output frames are synchronized to a super-frame that corresponds to a least common multiple frame in a conventional synchronizing and mixing system.

Abstract: A multistream data packet transfer apparatus and method receives data for at least one stream of multistream data from multiple fragments of memory, over a bus from a first processor. The first processor stores multistream data in the fragmented memory. An interface controller, such as any suitable logic and /or software, evaluates the received data to determine which received data is usable data for a second processor. A data packer removes unusable data and packs the usable data in fixed sized units to form a data packet for the second processor. The data packer packs data received from different fragments of memory as a single packet for use by a DSP requesting the information.

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Abstract: A universal asynchronous receiver transmitter (UART) emulation stage for modem communication uses a digital signal processor containing a software UART control program for sending UART control signals to hardware based UART emulation circuitry. The software UART control program communicates to a modem application interface program that is under control of a host processor. The UART emulation circuitry that is responsive to the control signals from the digital signal processor, includes dedicated transmit and receive FIFO buffer memory for storing modem data and also includes interrupt generation logic to generate an interrupt for the digital signal processor when the received FIFO buffer memory is at a predetermined threshold. The UART emulation circuitry also includes programmable control logic for facilitating host processor interrupt pacing to maintain high compatibility with legacy applications, namely DOS based applications.

Abstract: A method and apparatus for memory allocation in a multi-processor system is accomplished by mapping portions of a shared memory to a first and second processor. The mapping is performed such that either of the processors' portions can be enlarged or reduced based on the memory that is located between the portions allocated to the processors. When a processor requests additional memory and there is sufficient free memory between the processors' respective portions, the appropriate amount of the free memory is allocated to the requesting processor.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.