Abstract: A transmitter system including: a bidirectional signaling (BDS) network having first and second networks for carrying first and second carrier signals, and having a set of n phase synchronous location pairs (ai, bi); and also including tunable transmitter circuits for driving an antenna array, each tunable transmitter circuit having an output line for carrying an output signal and first and second input lines electrically connected to the first and second networks of the BDS network at locations of a corresponding one of the set of phase synchronous location pairs, and including a multiplier having a first input electrically connected to the first input line of that tunable transmitter circuit; a phase setting circuit electrically connected to the multiplier for controlling the phase of the output signal of that tunable transmitter circuit; and an amplitude setting circuit for controlling the amplitude of the output signal of that tunable transmitter circuit.

Abstract: A transmitter system including: a bidirectional signaling (BDS) network having first and second networks for carrying first and second carrier signals, and having a set of n phase synchronous location pairs (ai, bi),; and also including tunable transmitter circuits for driving an antenna array, each tunable transmitter circuit having an output line for carrying an output signal and first and second input lines electrically connected to the first and second networks of the BDS network at locations of a corresponding one of the set of phase synchronous location pairs, and including a multiplier having a first input electrically connected to the first input line of that tunable transmitter circuit; a phase setting circuit electrically connected to the multiplier for controlling the phase of the output signal of that tunable transmitter circuit; and an amplitude setting circuit for controlling the amplitude of the output signal of that tunable transmitter circuit.

Abstract: The present invention is directed toward a radio, and method for receiving radio frequency signals. The radio comprises an input signal at a first intermediate frequency, an intermediate sampling architecture, a quantizer and a baseband converter. The intermediate frequency sampling architecture comprises receiving the input signal, passing the first intermediate frequency signal through a first filter characterized by steep selectivity and narrow bandpass, converting the filtered signal to a second intermediate frequency and passing the second intermediate frequency signal through a second filter having a bandpass characteristic, but without the steep selectivity characterizing the first filter. The radio further comprises a third filter following the baseband conversion which filters out adjacent channel harmonics to obtain a wanted data signal.

Abstract: The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.

Abstract: An up to 3× breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver.

Abstract: A system, method and apparatus are disclosed for common-mode voltage feedback. The preferred system includes a plurality of differential circuits, a corresponding plurality of common-mode voltage detectors, a corresponding plurality of buffer circuits, and a common-mode control circuit. Each differential circuit is operative to produce a first differential output voltage and a second differential output voltage. Each corresponding common-mode voltage detector is operative to provide a common-mode voltage from the first differential output voltage and the second differential output voltage. The common-mode control circuit provides a control voltage signal from the common-mode voltage and from a reference voltage. Each buffer circuit is operative to adjust the corresponding common-mode voltage using the control voltage signal to provide a common-mode feedback voltage signal to the corresponding differential circuit.

Abstract: A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.

Abstract: A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.

Abstract: The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.

Abstract: The present invention is directed toward a radio, and method for receiving radio frequency signals. The radio comprises an input signal at a first intermediate frequency, an intermediate sampling architecture, a quantizer and a baseband converter. The intermediate frequency sampling architecture comprises receiving the input signal, passing the first intermediate frequency signal through a first filter characterized by steep selectivity and narrow bandpass, converting the filtered signal to a second intermediate frequency and passing the second intermediate frequency signal through a second filter having a bandpass characteristic, but without the steep selectivity characterizing the first filter. The radio further comprises a third filter following the baseband conversion which filters out adjacent channel harmonics to obtain a wanted data signal.

Abstract: A system and method for limiting and filtering a combined signal is provided. An embodiment of the system comprises at least one soft limiter and filter that soft limits and filters the combined signal to output a soft limited and filtered signal. An embodiment of the method comprises soft limiting and filtering the combined signal to output the soft limited and filtered signal.

Abstract: A system, method and apparatus are disclosed for common-mode voltage feedback. The preferred system includes a plurality of differential circuits, a corresponding plurality of common-mode voltage detectors, a corresponding plurality of buffer circuits, and a common-mode control circuit. Each differential circuit is operative to produce a first differential output voltage and a second differential output voltage. Each corresponding common-mode voltage detector is operative to provide a common-mode voltage from the first differential output voltage and the second differential output voltage. The common-mode control circuit provides a control voltage signal from the common-mode voltage and from a reference voltage. Each buffer circuit is operative to adjust the corresponding common-mode voltage using the control voltage signal to provide a common-mode feedback voltage signal to the corresponding differential circuit.

Abstract: An up to 3× breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver.

Abstract: A sampling device for sampling an input signal in response to a pulse train of a sample signal. The sampling device includes a sampling transistor for creating samples in response to the sample signal. The sampling transistor has an impedance corresponding with the difference between the gate to source voltage and the threshold voltage of the sampling transistor. The sampling device also includes a control device for generating a control signal. The control device includes a bootstrap reference voltage source for providing a reference voltage in response to the sample signal, and a control circuit for generating the control circuit voltage in response to the sample signal. By this design, the control signal comprises the sum of the input signal and the sampling threshold voltage, the control signal comprises the sum of control circuit voltage and the reference voltage, and the gate to source voltage comprises the difference between the control signal and the input signal.

Abstract: A feed-forward compensated negative feedback circuit comprises an operational amplifier having an inverting and a non-inverting input and an output. A feedback element is connected between the output of the operational amplifier and its inverting input to form a negative feedback loop. The inverting input of the op-amp is driven with a first transconductance amplifier which produces an output current proportional to an input voltage. A feed-forward transconductance amplifier receives the input voltage and produces an inverted output current proportional to the input voltage. A feed-forward current is injected at the output of the operational amplifier. By providing at the output of the op-amp the current it would be required to carry over the feedback loop, a voltage differential at the op-amp inputs is avoided, thus eliminating parasitic current flows across the parasitic input capacitance and thereby improving the circuits overall performance.

Abstract: A multiple differential pair circuit is disclosed having a transconductance, gm, proportional to the bias current, I0, for any transistor technology. The transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit operate in a non-exponential voltage-current (V-I) region. As multiple differential pair circuits are linearized, the effective transconductance, gm, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Methods and apparatus are disclosed that provide a linear transconductance, gm, with respect to the bias current, I0, using differential pairs of transistors where each transistor operates in a non-exponential voltage-current (V-I) region, such as MOS transistors.