Abstract: An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node a charge sharing transistor coupled between the photodiode and the floating diffusion node, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. Two current memory circuits are coupled to the input of the select transistor and are configured to sense and output respective signals indicative of levels of noise in the detector element.

Abstract: An image sensor includes a pixel-circuit and circuitry. The pixel-circuit includes a PD that accumulates charge responsively to incident light and a FD that stores the charge. The circuitry serially (i) connects the PD and a supply rail to the FD and sends a first FD voltage, (ii) disconnects the supply rail from the FD and sends a second FD voltage, (iii) disconnects the PD from the FD and sends a third FD voltage, (iv) waits a preset exposure time, (v) connects the supply rail to the FD and sends a fourth FD voltage, (vi) disconnects the supply rail from the FD and sends a fifth FD voltage, and (vii) connects the PD to the FD and sends a sixth FD voltage. The circuitry estimates incident light energy responsively to (i) the FD voltages, and (ii) a capacitance ratio defined over at least capacitances of the FD and the PD.

Abstract: An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node a charge sharing transistor coupled between the photodiode and the floating diffusion node, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. Two current memory circuits are coupled to the input of the select transistor and are configured to sense and output respective signals indicative of levels of noise in the detector element.

Abstract: An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node connected to one of the terminals of the photodiode, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. A current memory circuit is coupled to the input of the select transistor and is configured to sense and output a signal indicative of a level of noise in the detector element.

Abstract: An image sensor includes a logic die, including column readout circuits, and a sensor die, overlaid on the logic die and including bitlines connected to the column readout circuits and an array of detector elements. Each detector element includes a photodiode having cathode and anode terminals and a floating diffusion node connected to one of the terminals of the photodiode. A first reset transistor is coupled between the floating diffusion node and a reset voltage. A source follower transistor has an input connected to the floating diffusion node and an output connect to a first terminal of an output capacitor having first and second terminals, with the first terminal. A second reset transistor is coupled between a second terminal of the output capacitor and the reset voltage. A select transistor is coupled between the second terminal of the output capacitor and one of the bitlines.

Abstract: A chirped illumination LIDAR system having a transmitter that may include a pulsed radiation illuminator that is followed by a beam forming optics. The transmitter may be configured to output, during each illumination period of a sub-group of illumination periods, a first plurality of radiation pulses that form a decimated chirp sequence of radiation pulses; the decimated chirp sequence is a sparse representation of a chirp signal. A receiver of the system may be configured to receive, during each reception period of a sub-group of reception periods, one or more received light pulses from one or more objects that were illuminated by the one or more radiation pulses transmitted during each illumination period.

Abstract: A LIDAR system includes a transmitter, a receiver, and a processor. The transmitter directs a sequence of illumination pulses toward a scene. The receiver including an array of photodetectors, which receive optical radiation reflected from the scene and output respective signals in response to the received optical radiation, a shutter which modulates the signals output by the photodetectors by applying a chirp shutter function, having a selected chirp period, to the signals, and a readout circuit, which samples and digitizes the modulated signals in each of a plurality of sampling windows, which span the chirp period, thereby generating a corresponding plurality of digitized output signals. The processor selects respective sampling windows for the photodetectors, and processes the digitized output signals in the selected respective sampling windows to generate a depth map of the scene.

Abstract: There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.

Abstract: There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.

Abstract: A LIDAR system that may include a transmitter and a receiver. The LIDAR system may include a transmitter and a receiver that may include an array of neuromorphic pixels and multiple accumulators. Each neuromorphic pixel may include multiple subpixels, an analog adder and a comparator; wherein for each reception period the analog adder is configured to generate an analog adder signal by adding detection signals from subpixels that are expected to receive at least one received light pulse during the reception period; wherein for each reception period the analog adder signal is indifferent to subpixels that are not expected to receive any received light pulses during the reception period; and wherein the comparator is configured to provide pixel output signals by comparing the analog adder signal to a threshold.

Abstract: A method for determining a temperature of a pixel; wherein the method includes supplying, by a current supply circuit and to the pixel, a bias current of a first value during a first period; changing, by the current supply circuit, a value of the pixel bias current to a second value; supplying, by the current supply circuit and to the pixel, a bias current of a second value during a second period; wherein the first value differs from the second value; reading, by a readout circuit that is coupled to the pixel, at a first point of time, a first output voltage of the pixel; wherein the first point in time occurs during the first period or the second period; and reading, by the readout circuit, at a second point of time that differs from the first point in time, a second output voltage of the pixel; wherein the second point in time occurs during the first period or the second period; wherein a difference between the first and second output voltage is indicative of a temperature of the pixel.

Abstract: An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

Abstract: A device comprising a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit; wherein the readout circuit comprises a current control circuit and a comparator; wherein the current control circuit is configured to (a) charge the current control circuit to a pixel affected charge using at least a pixel affected current that is indicative of an electrical parameter of the pixel and (b) drain, based on the pixel affected charge, a current control circuit current during a comparison period; wherein the comparator is configured to compare, during the comparison period, between a pixel affected voltage and a reference signal that changes during the comparison period and to provide at least one pulse that has is indicative of a value of the pixel affected voltage.

Abstract: A LIDAR system that may include a transmitter and a receiver.

Abstract: An ADC that may include PWM modulators.

Abstract: A low dropout voltage regulator includes: a pass element connected between an input terminal and an output terminal of the low dropout voltage regulator; an error amplifier driving a control terminal of the pass element; a first compensation element connected to the output terminal of the low dropout voltage regulator; and a compensation circuit connected to a control terminal (of the first compensation element, wherein the compensation circuit is configured to control a trans-conductance of the first compensation element in accordance with a noise compensation criterion.

Abstract: A device that may include a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit via coupling lines that comprises an output line and a reset line; wherein the readout circuit comprises (a) a comparator that is configured to track a coupling line electrical parameter to generate a pulse that is responsive to value of the electrical parameter, and (b) a pulse width to digital converter for outputting a digital output signal that is responsive to a width of the pulse.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

Abstract: A device that may include a pixel, an output conductor and a charge accelerator; wherein during a readout phase of the pixel, the pixel is configured to attempt to charge the output conductor to a pixel reset voltage and the charge accelerator is configured to perform a sampling operation and a charge operation; wherein during the sampling operation the charge accelerator is configured to sample a change in an output conductor voltage; wherein during the charge operation the charge accelerator is configured to output a charge accelerator output signal that is responsive to the change of the output conductor voltage, wherein once provided, the charge accelerator output signal accelerates a charging of the output conductor to a target voltage that is proximate to the pixel reset voltage; wherein the sampling operation and the charge operation do not overlap.