Patents by Inventor Vladimir M. Gushchin

Vladimir M. Gushchin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7065750
    Abstract: Precise exceptions handling in the optimized binary translated code is achieved by transitioning execution to the non-optimized step-by-step foreign code execution means in accordance with one of the several coherent foreign states designated during the optimized translation of the foreign code. A method to improve the operation by avoiding complete foreign state updates in the optimized code, an apparatus to track the switching between the states and a method to recompute the complete foreign state in accordance to the current state identification, execution context and additional documentation provided during the translation time are proposed.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: June 20, 2006
    Assignee: Elbrus International
    Inventors: Boris A. Babaian, Andrew V. Yakushev, Sergey A. Rozhkov, Vladimir M. Gushchin
  • Publication number: 20020092002
    Abstract: The present invention provides a system and method for determining the cause of an exception and for reliably handling precise exceptions in a computer system that executes a plurality of operations in parallel. Binary compilation techniques are used to port code from a foreign architecture to a host architecture but in order to exploit the parallelism of the host processor architecture in binary translated code, the code must optimized by extracting the inherent parallelism of the foreign code while maintaining precise exceptions. Because the optimization process violates precise exception order, the host computer system uses a speculative mode of execution whereby the host computer system puts a speculative value into the destination register. To denote that a speculative value is stored in the register, an additional bit is associated with every host register to indicate that the operand is speculative.
    Type: Application
    Filed: April 18, 2001
    Publication date: July 11, 2002
    Inventors: Boris A. Babaian, Andrew V. Yakushev, Sergey A. Rozhkov, Vladimir M. Gushchin