Patents by Inventor Vladimir Noveski

Vladimir Noveski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037941
    Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Noveski, Milind Pravin Shah, Rajneesh Kumar
  • Patent number: 9806063
    Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Vladimir Noveski, Jie Fu, Ahmer Raza Syed, Milind Pravin Shah, Omar James Bchir
  • Publication number: 20160322332
    Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Vladimir Noveski, Jie Fu, Ahmer Raza Syed, Milind Pravin Shah, Omar James Bchir
  • Publication number: 20160172299
    Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.
    Type: Application
    Filed: January 30, 2015
    Publication date: June 16, 2016
    Inventors: Vladimir Noveski, Milind Pravin Shah, Rajneesh Kumar
  • Publication number: 20160148864
    Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.
    Type: Application
    Filed: May 4, 2015
    Publication date: May 26, 2016
    Inventors: Jie Fu, David Fraser Rae, Manuel Aldrete, Vladimir Noveski, Chin-Kwan Kim
  • Patent number: 9258880
    Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Publication number: 20140013855
    Abstract: A deflection sensor is disclosed herein. The deflection sensor includes a nanotube film adjacent to a substrate, and first and second contacts electrically connectable with the nanotube film. Methods of making and using the deflection sensor are also disclosed.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Inventors: Mohammad M. FARAHANI, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
  • Publication number: 20130341076
    Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
    Type: Application
    Filed: August 22, 2013
    Publication date: December 26, 2013
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Patent number: 8604353
    Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Patent number: 8586393
    Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: November 19, 2013
    Assignee: Intel Corporation
    Inventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
  • Patent number: 8414677
    Abstract: The invention provides a method of forming a dense, shaped article, such as a crucible, formed of a refractory material, the method comprising the steps of placing a refractory material having a melting point of at least about 2900° C. in a mold configured to form the powder into an approximation of the desired shape. The mold containing the powder is treated at a temperature and pressure sufficient to form a shape-sustaining molded powder that conforms to the shape of the mold, wherein the treating step involves sintering or isostatic pressing. The shape-sustaining molded powder can be machined into the final desired shape and then sintered at a temperature and for a time sufficient to produce a dense, shaped article having a density of greater than about 90% and very low open porosity. Preferred refractory materials include tantalum carbide and niobium carbide.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: April 9, 2013
    Assignee: North Carolina State University
    Inventors: Raoul Schlesser, Rafael F. Dalmau, Vladimir Noveski, Zlatko Sitar
  • Publication number: 20120193734
    Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Applicant: Intel Corporation
    Inventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
  • Publication number: 20120152601
    Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
    Type: Application
    Filed: January 19, 2012
    Publication date: June 21, 2012
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Patent number: 8186051
    Abstract: Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Patent number: 8174084
    Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
  • Patent number: 7678195
    Abstract: A method of growing bulk single crystals of an AlN on a single crystal seed is provided, wherein an AlN source material is placed within a crucible chamber in spacial relationship to a seed fused to the cap of the crucible. The crucible is heated in a manner sufficient to establish a temperature gradient between the source material and the seed with the seed at a higher temperature than the source material such that the outer layer of the seed is evaporated, thereby cleaning the seed of contaminants and removing any damage to the seed incurred during seed preparation. Thereafter, the temperature gradient between the source material and the seed is inverted so that the source material is sublimed and deposited on the seed, thereby growing a bulk single crystal of AlN.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: March 16, 2010
    Assignee: North Carolina State University
    Inventors: Raoul Schlesser, Vladimir Noveski, Zlatko Sitar
  • Publication number: 20090324859
    Abstract: The invention provides a method of forming a dense, shaped article, such as a crucible, formed of a refractory material, the method comprising the steps of placing a refractory material having a melting point of at least about 2900° C. in a mold configured to form the powder into an approximation of the desired shape. The mold containing the powder is treated at a temperature and pressure sufficient to form a shape-sustaining molded powder that conforms to the shape of the mold, wherein the treating step involves sintering or isostatic pressing. The shape-sustaining molded powder can be machined into the final desired shape and then sintered at a temperature and for a time sufficient to produce a dense, shaped article having a density of greater than about 90% and very low open porosity. Preferred refractory materials include tantalum carbide and niobium carbide.
    Type: Application
    Filed: September 10, 2009
    Publication date: December 31, 2009
    Inventors: Raoul Schlesser, Rafael F. Dalmau, Vladimir Noveski, Zlatko Sitar
  • Patent number: 7632454
    Abstract: The invention provides a method of forming a dense, shaped article, such as a crucible, formed of a refractory material, the method comprising the steps of placing a refractory material having a melting point of at least about 2900° C. in a mold configured to form the powder into an approximation of the desired shape. The mold containing the powder is treated at a temperature and pressure sufficient to form a shape-sustaining molded powder that conforms to the shape of the mold, wherein the treating step involves sintering or isostatic pressing. The shape-sustaining molded powder can be machined into the final desired shap and then sintered at a temperature and for a time sufficient to produce a dense, shaped article having a density of greater than about 90% and very low open porosity. Preferred refractory materials include tantalum carbide and niobium carbide.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: December 15, 2009
    Assignee: North Carolina State University
    Inventors: Raoul Schlesser, Rafael F. Dalmau, Vladimir Noveski, Zlatko Sitar
  • Publication number: 20090242247
    Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
  • Publication number: 20080237844
    Abstract: A microelectronic package includes a package substrate (110, 310, 410), a plurality of dies (120, 610, 630) arranged in a stack (150, 350, 450) above the package substrate, with a first die (121) located above the package substrate at a bottom (151) of the stack and an uppermost die (122) located at a top (152) of the stack, and a plurality of heat spreaders (130, 330, 430, 620) stacked above the first die, with a first heat spreader (131) located above the uppermost die. One of the plurality of heat spreaders is located between each pair of adjacent dies. Each one of the plurality of heat spreaders has an extending portion (132) that extends laterally beyond an edge (123) of an adjacent die, and at least one of the plurality of heat spreaders both provides electrical interconnectivity and thermal conductivity.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan