Patents by Inventor Vladimir NUSIMOVICH

Vladimir NUSIMOVICH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9906355
    Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: February 27, 2018
    Assignee: NXP USA, Inc.
    Inventors: Michael Priel, Leonid Fleshel, Roman Mostinski, Vladimir Nusimovich
  • Patent number: 9652572
    Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 16, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael Priel, Eliya Babitsky, Asher Berkovitz, Vladimir Nusimovich
  • Publication number: 20150338464
    Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.
    Type: Application
    Filed: January 9, 2013
    Publication date: November 26, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael PRIEL, Leonid FLESHEL, Roman MOSTINSKI, Vladimir NUSIMOVICH
  • Publication number: 20150339413
    Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.
    Type: Application
    Filed: January 8, 2013
    Publication date: November 26, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: MICHAEL PRIEL, ELIYA BABITSKY, ASHER BERKOVITZ, VLADIMIR NUSIMOVICH