Abstract: A current mirror circuit includes a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor, a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current, a sample and hold circuit having an input connected to the gate of the first transistor, a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency to attenuate bias noise from the first transistor in a second output current from the second transistor.

Abstract: A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal.

Abstract: A gyroscopic sensor includes a vibratory gyroscopic sensor element, first and second drive electrodes positioned proximate to the vibratory gyroscopic sensor element, and a drive circuit operatively connected to the first and second drive electrodes. The drive circuit is configured to generate a stepped sinusoidal waveform having a plurality of steps, each step having a predetermined duration and each step having an output level in a plurality of predetermined output levels for the stepped sinusoidal waveform including at least three positive output levels and at least three negative output levels to generate oscillation of the vibratory gyroscopic sensor element at a predetermined frequency.

Abstract: A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.

Abstract: A digital phase lock loop circuit includes a phase detector, loop filter, finite impulse response filter (FIR), a plurality of digital to analog converters (DACs), a voltage controlled oscillator (VCO), and a divider. The FIR filter includes a predetermined number of taps, where each tap is connected to an input of one DAC in the plurality of DACs. The FIR filter attenuates high-frequency quantization error in a digital control signal that the plurality of DACs converts to an analog control signal for the VCO. The FIR filtered control signal reduces or eliminates quantization noise higher-frequency components that would otherwise be generated as DC quantization noise in a feedback signal generated by the divider.

Abstract: A current mirror circuit includes a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor, a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current, a sample and hold circuit having an input connected to the gate of the first transistor, a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency to attenuate bias noise from the first transistor in a second output current from the second transistor.

Abstract: A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.

Abstract: A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal.

Abstract: A digital phase lock loop circuit includes a phase detector, loop filter, finite impulse response filter (FIR), a plurality of digital to analog converters (DACs), a voltage controlled oscillator (VCO), and a divider. The FIR filter includes a predetermined number of taps, where each tap is connected to an input of one DAC in the plurality of DACs. The FIR filter attenuates high-frequency quantization error in a digital control signal that the plurality of DACs converts to an analog control signal for the VCO. The FIR filtered control signal reduces or eliminates quantization noise higher-frequency components that would otherwise be generated as DC quantization noise in a feedback signal generated by the divider.

Abstract: A gyroscopic sensor includes a vibratory gyroscopic sensor element, first and second drive electrodes positioned proximate to the vibratory gyroscopic sensor element, and a drive circuit operatively connected to the first and second drive electrodes. The drive circuit is configured to generate a stepped sinusoidal waveform having a plurality of steps, each step having a predetermined duration and each step having an output level in a plurality of predetermined output levels for the stepped sinusoidal waveform including at least three positive output levels and at least three negative output levels to generate oscillation of the vibratory gyroscopic sensor element at a predetermined frequency.