Patents by Inventor Vladimir P. Zolotov
Vladimir P. Zolotov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9798843Abstract: A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.Type: GrantFiled: July 15, 2015Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Jin Hu, SheshaShayee K. Raghunathan, Debjit Sinha, Vladimir P. Zolotov
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Publication number: 20170017743Abstract: A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.Type: ApplicationFiled: July 15, 2015Publication date: January 19, 2017Inventors: Jin Hu, SheshaShayee K. Raghunathan, Debjit Sinha, Vladimir P. Zolotov
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Patent number: 8510696Abstract: Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.Type: GrantFiled: March 16, 2012Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Chandramouli Visweswariah, Jinjun Xiong, Vladimir P. Zolotov
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Patent number: 8266565Abstract: Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.Type: GrantFiled: January 29, 2010Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventors: Chandramouli Visweswariah, Jinjun Xiong, Vladimir P. Zolotov
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Publication number: 20120192136Abstract: Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chandramouli Visweswariah, Jinjun Xiong, Vladimir P. Zolotov
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Publication number: 20110191730Abstract: Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chandramouli Visweswariah, Jinjun Xiong, Vladimir P. Zolotov
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Patent number: 7251797Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.Type: GrantFiled: November 22, 2004Date of Patent: July 31, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Murat R. Becer, Ilan Algor, Amir Grinshpon, Rafi Levy, Chanhee Oh, Rajendran V. Panda, Vladimir P. Zolotov
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Patent number: 7127384Abstract: A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.Type: GrantFiled: August 27, 2002Date of Patent: October 24, 2006Assignee: Freescale semiconductor, Inc.Inventors: Vladimir P. Zolotov, Rajendran V. Panda, Sergey V. Gavrilov, Alexey L. Glebov, Yury B. Egorov, Dmitry Y. Nadexhin
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Patent number: 6819538Abstract: The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.Type: GrantFiled: May 15, 2001Date of Patent: November 16, 2004Assignee: Freescale Semiconductor, Inc.Inventors: David T. Blaauw, Rajendran V. Panda, Rajat Chaudhry, Vladimir P. Zolotov, Ravindraraj Ramaraju
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Patent number: 6799153Abstract: A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor.Type: GrantFiled: April 20, 2000Date of Patent: September 28, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Supamas Sirichotiyakul, David T. Blaauw, Chanhee Oh, Vladimir P. Zolotov, Rafi Levy
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Publication number: 20030061016Abstract: Method for generating a set of switching vectors where each vector S1-Si causes the output X to transition in the predetermined way provided that the input A transitions in the selected way. This method may be used for any electrical circuit cluster, including the simple one illustrated in FIG. 3. This method handles any number of side inputs, gate clusters which have feedback within the gate cluster, and gate clusters which have internal nodes that may be in a third state other than a logic level one or a logic level zero (e.g. a high impedance state).Type: ApplicationFiled: August 29, 2001Publication date: March 27, 2003Inventors: David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Rafi Levy, Vladimir P. Zolotov
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Publication number: 20020171407Abstract: The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Inventors: David T. Blaauw, Rajendran V. Panda, Rajat Chaudhry, Vladimir P. Zolotov, Ravindraraj Ramaraju