Patents by Inventor Vladimir Pentkovski
Vladimir Pentkovski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9632790Abstract: A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.Type: GrantFiled: December 26, 2012Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexey Y. Sivtsov, Yuriy V Baida, Alexander V Butuzov, Bob Babayan, Vladimir Pentkovski
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Publication number: 20140208074Abstract: In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2012Publication date: July 24, 2014Inventors: Boris A. Babayan, Vladimir Pentkovski, Jayesh Iyer, Nikolay Kosarev, Sergey Y. Shishlov, Alexander V. Butuzov, Alexey Y. Sivtsov
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Patent number: 8065555Abstract: A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.Type: GrantFiled: February 28, 2006Date of Patent: November 22, 2011Assignee: Intel CorporationInventors: Subramaniam Maiyuran, Varghese George, Vladimir Pentkovski, Sanjib Sarkar, Marina Sherman
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Patent number: 7516307Abstract: A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute differences (PSAD) instruction having an opcode format to identify a set of packed data operands. The decode unit initiates a sequence of operations on the set of packed data operands in response to decoding the PSAD instruction. An execution unit performs a first operation of the sequence of operations initiated by the decode logic, and a bus provides the execution unit with the set of packed data operands as identified in accordance with the opcode format.Type: GrantFiled: November 6, 2001Date of Patent: April 7, 2009Assignee: Intel CorporationInventors: Mohammad A. Abdallah, Vladimir Pentkovski
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Patent number: 7467286Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.Type: GrantFiled: May 9, 2005Date of Patent: December 16, 2008Assignee: Intel CorporationInventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Publication number: 20070226589Abstract: A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.Type: ApplicationFiled: February 28, 2006Publication date: September 27, 2007Inventors: Subramaniam Maiyuran, Varghese George, Vladimir Pentkovski, Sanjib Sarkar, Marina Sherman
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Patent number: 7216138Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.Type: GrantFiled: February 14, 2001Date of Patent: May 8, 2007Assignee: Intel CorporationInventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, legal representative, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar, Hsien-Cheng E. Hsieh, deceased
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Patent number: 6978357Abstract: A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.Type: GrantFiled: July 24, 1998Date of Patent: December 20, 2005Assignee: Intel CorporationInventors: Lance Hacking, Shreekant Thakkar, Thomas Huff, Vladimir Pentkovski, Hsien-Cheng E. Hsieh
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Patent number: 6976131Abstract: A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.Type: GrantFiled: August 23, 2002Date of Patent: December 13, 2005Assignee: Intel CorporationInventors: Vladimir Pentkovski, Vivek Garg, Narayanan S. Iyer, Jagannath Keshava
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Patent number: 6970994Abstract: A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.Type: GrantFiled: May 8, 2001Date of Patent: November 29, 2005Assignee: Intel CorporationInventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Publication number: 20050216706Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.Type: ApplicationFiled: May 9, 2005Publication date: September 29, 2005Inventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant Thakkar
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Publication number: 20040268094Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format.Type: ApplicationFiled: February 14, 2001Publication date: December 30, 2004Inventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Patent number: 6801208Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.Type: GrantFiled: December 27, 2000Date of Patent: October 5, 2004Assignee: Intel CorporationInventors: Jagganath Keshava, Vladimir Pentkovski, Subramaniam Maiyuran, Salvador Palanca, Hsin-Chu Tsai
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Patent number: 6748512Abstract: A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.Type: GrantFiled: December 8, 2000Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Deep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan
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Publication number: 20040039880Abstract: A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Inventors: Vladimir Pentkovski, Vivek Garg, Narayanan S. Iyer, Jagannath Keshava
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Patent number: 6643745Abstract: A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.Type: GrantFiled: March 31, 1998Date of Patent: November 4, 2003Assignee: Intel CorporationInventors: Salvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai, Subramaniam Maiyuran, Jagannath Keshava, Hsien-Hsin Lee, Steve Spangler, Suresh Kuttuva, Praveen Mosur
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Patent number: 6584547Abstract: A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.Type: GrantFiled: March 9, 2001Date of Patent: June 24, 2003Assignee: Intel CorporationInventors: Salvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai
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Patent number: 6502115Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.Type: GrantFiled: April 27, 2001Date of Patent: December 31, 2002Assignee: Intel CorporationInventors: Mohammad A. F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Patent number: 6480868Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.Type: GrantFiled: April 27, 2001Date of Patent: November 12, 2002Assignee: Intel CorporationInventors: Mohammad A.F. Abdallah, Hsien-Cheng E. Hsieh, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
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Publication number: 20020116576Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.Type: ApplicationFiled: December 27, 2000Publication date: August 22, 2002Inventors: Jagannath Keshava, Vladimir Pentkovski, Subramaniam Maiyuran, Salvador Palanca, Hsin-Chu Tsai