Patents by Inventor Vladimir Rumennik
Vladimir Rumennik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6828631Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: May 5, 2004Date of Patent: December 7, 2004Assignee: Power Integrations, IncInventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Publication number: 20040217419Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: June 3, 2004Publication date: November 4, 2004Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Aiit
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Publication number: 20040207012Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: May 5, 2004Publication date: October 21, 2004Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6800903Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: September 20, 2001Date of Patent: October 5, 2004Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6787437Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: June 6, 2002Date of Patent: September 7, 2004Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6777749Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: February 18, 2003Date of Patent: August 17, 2004Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6768172Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: February 18, 2003Date of Patent: July 27, 2004Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6724041Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: October 21, 2002Date of Patent: April 20, 2004Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6633065Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: September 20, 2001Date of Patent: October 14, 2003Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Publication number: 20030151093Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: February 18, 2003Publication date: August 14, 2003Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Publication number: 20030151101Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: February 18, 2003Publication date: August 14, 2003Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Patent number: 6600182Abstract: A MOSFET that provides high current conduction at high frequency includes a deposited layer over a substrate of a first conductivity type, with source and drain regions adjoining a top surface of the epitaxial layer. The drain region has a first portion that extends vertically through the epitaxial layer to connect to the substrate and a second portion that extends laterally along the top surface. A first region is disposed in the epitaxial layer between the extended region and the source region. An insulated gate is located above the first region between the source region and the second portion of the drain region. A drain metal layer contacts a bottom surface of the substrate, and a source metal layer that substantially covers the top surface connect to the source region.Type: GrantFiled: September 26, 2001Date of Patent: July 29, 2003Inventor: Vladimir Rumennik
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Patent number: 6570219Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: May 17, 2000Date of Patent: May 27, 2003Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Publication number: 20030057459Abstract: A MOSFET that provides high current conduction at high frequency includes a deposited layer over a substrate of a first conductivity type, with source and drain regions adjoining a top surface of the epitaxial layer. The drain region has a first portion that extends vertically through the epitaxial layer to connect to the substrate and a second portion that extends laterally along the top surface. A first region is disposed in the epitaxial layer between the extended region and the source region. An insulated gate is located above the first region between the source region and the second portion of the drain region. A drain metal layer contacts a bottom surface of the substrate, and a source metal layer that substantially covers the top surface connect to the source region.Type: ApplicationFiled: September 26, 2001Publication date: March 27, 2003Inventor: Vladimir Rumennik
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Publication number: 20030042541Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: October 21, 2002Publication date: March 6, 2003Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald Ray Disney, Janardhanan S. Ajit
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Publication number: 20030025155Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: September 20, 2001Publication date: February 6, 2003Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Publication number: 20020153556Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: June 6, 2002Publication date: October 24, 2002Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald Ray Disney, Janardhanan S. Ajit
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Publication number: 20020053698Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: September 20, 2001Publication date: May 9, 2002Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald Ray Disney
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Publication number: 20020050613Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: ApplicationFiled: September 20, 2001Publication date: May 2, 2002Applicant: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald Ray Disney, Janardhanan S. Ajit
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Patent number: 6207994Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.Type: GrantFiled: February 5, 1999Date of Patent: March 27, 2001Assignee: Power Integrations, Inc.Inventors: Vladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit