Abstract: A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications channel.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.

Abstract: A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshold level corresponding to a first threshold value. The threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provides the first threshold value to the sampling circuit.

Abstract: A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

Abstract: A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a second threshold. A drive strength of the equalizing transmitter and a drive strength of an equalizing signal driver within the equalizer are adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: An improved SR latch has a two stages. A generation block generates Q and {overscore (Q)} signals from a set signal and a reset signal. The generation block also has an inactive state. A storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals at the voltage level that was output by the generation block prior to when the generation block blocks becomes inactive. In another embodiment, an improved D flip-flop has a sensing block with the improved SR latch of the present invention.