Patents by Inventor Vladimir T. Khlobystov

Vladimir T. Khlobystov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and methods for execution of computer instructions
    Patent number: 6099158
    Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: August 8, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Valery Y. Gorshtein, Vladimir T. Khlobystov
  • Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization
    Patent number: 5963461
    Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: October 5, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Valery Y. Gorshtein, Vladimir T. Khlobystov
  • Executing computer instrucrions by circuits having different latencies
    Patent number: 5844830
    Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles occur with no instructions started, subsequent fast instructions are executed by the fast execution path.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: December 1, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Valery Y. Gorshtein, Vladimir T. Khlobystov