Patents by Inventor Vladimir Tsukanov
Vladimir Tsukanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10439483Abstract: In a switching converter having an inductive load, a current may flow through the body diode of a transistor even though the gate of the transistor is being controlled to keep the transistor off. Then when the other transistor of the switch leg is turned on, a reverse recovery current flows in the reverse direction through the body diode. To reduce switching losses associated with such current flows, a gate driver integrated circuit detects when current flow through the body diode rises above a threshold current. The gate driver integrated circuit then controls the transistor to turn on. Then when the other transistor of the switch leg is made to turn on, the gate driver first turns the transistor off. When the gate-to-source voltage of the turning off transistor drops below a threshold voltage, then the gate driver integrated circuit allows and controls the other transistor to turn on.Type: GrantFiled: October 2, 2018Date of Patent: October 8, 2019Assignee: Littelfuse, Inc.Inventors: Anatoliy V. Tsyrganovich, Leonid A. Neyman, Md Abdus Sattar, Vladimir Tsukanov
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Publication number: 20190260281Abstract: In a switching converter having an inductive load, a current may flow through the body diode of a transistor even though the gate of the transistor is being controlled to keep the transistor off. Then when the other transistor of the switch leg is turned on, a reverse recovery current flows in the reverse direction through the body diode. To reduce switching losses associated with such current flows, a gate driver integrated circuit detects when current flow through the body diode rises above a threshold current. The gate driver integrated circuit then controls the transistor to turn on. Then when the other transistor of the switch leg is made to turn on, the gate driver first turns the transistor off. When the gate-to-source voltage of the turning off transistor drops below a threshold voltage, then the gate driver integrated circuit allows and controls the other transistor to turn on.Type: ApplicationFiled: October 2, 2018Publication date: August 22, 2019Applicant: Littelfuse, Inc.Inventors: Anatoliy V. Tsyrganovich, Leonid A. Neyman, Md Abdus Sattar, Vladimir Tsukanov
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Patent number: 10090751Abstract: In a switching converter having an inductive load, a current may flow through the body diode of a transistor even though the gate of the transistor is being controlled to keep the transistor off. Then when the other transistor of the switch leg is turned on, a reverse recovery current flows in the reverse direction through the body diode. To reduce switching losses associated with such current flows, a gate driver integrated circuit detects when current flow through the body diode rises above a threshold current. The gate driver integrated circuit then controls the transistor to turn on. Then when the other transistor of the switch leg is made to turn on, the gate driver first turns the transistor off. When the gate-to-source voltage of the turning off transistor drops below a threshold voltage, then the gate driver integrated circuit allows and controls the other transistor to turn on.Type: GrantFiled: February 21, 2018Date of Patent: October 2, 2018Assignee: IXYS, LLCInventors: Anatoliy V. Tsyrganovich, Leonid A. Neyman, Md Abdus Sattar, Vladimir Tsukanov
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Publication number: 20170125559Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.Type: ApplicationFiled: July 28, 2016Publication date: May 4, 2017Inventor: Vladimir Tsukanov
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Patent number: 9627521Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.Type: GrantFiled: July 28, 2016Date of Patent: April 18, 2017Assignee: IXYS CorporationInventor: Vladimir Tsukanov
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Patent number: 9419118Abstract: A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.Type: GrantFiled: November 3, 2015Date of Patent: August 16, 2016Assignee: IXYS CorporationInventor: Vladimir Tsukanov
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Patent number: 8900943Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.Type: GrantFiled: May 31, 2014Date of Patent: December 2, 2014Assignee: IXYS CorporationInventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
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Publication number: 20140273357Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.Type: ApplicationFiled: May 31, 2014Publication date: September 18, 2014Applicant: IXYS CorporationInventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
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Patent number: 8741709Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.Type: GrantFiled: May 23, 2011Date of Patent: June 3, 2014Assignee: IXYS CorporationInventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
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Patent number: 8344480Abstract: A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N? layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode.Type: GrantFiled: September 30, 2009Date of Patent: January 1, 2013Assignee: IXYS CorporationInventors: Kyoung-Wook Seok, Vladimir Tsukanov
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Publication number: 20110312137Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.Type: ApplicationFiled: May 23, 2011Publication date: December 22, 2011Applicant: IXYS CorporationInventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
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Publication number: 20100078674Abstract: A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N? layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode.Type: ApplicationFiled: September 30, 2009Publication date: April 1, 2010Applicant: IXYS CorporationInventors: Kyoung-Wook Seok, Vladimir Tsukanov
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Patent number: 7157338Abstract: A method for making a power device produces a power device comprising active cells having designs that vary depending on where they are located in the active area. Design variations include structural variations and variations in the material used to produce the cells.Type: GrantFiled: March 1, 2004Date of Patent: January 2, 2007Assignee: IXYS CorporationInventors: Nathan Zommer, Vladimir Tsukanov
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Patent number: 7063975Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. The substrate has a trench. First and second doped regions are provided proximate the upper surface of the substrate. A first source region is provided within the first doped region. A second source region is provided within the second doped region. A gate is provided between the first and second source regions. The gate includes a first portion extending downward into the trench. A depth of the trench is no more than a depth of the first doped region.Type: GrantFiled: October 3, 2003Date of Patent: June 20, 2006Assignee: IXYS CorporationInventors: Vladimir Tsukanov, Nathan Zommer
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Publication number: 20040232484Abstract: An active area of a power device comprises active cells having designs that vary depending on where they are located in the active area. Design variations include structural variations and variations in the material used to produce the cells.Type: ApplicationFiled: March 1, 2004Publication date: November 25, 2004Applicant: IXYS CorporationInventors: Nathan Zommer, Vladimir Tsukanov
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Publication number: 20040124489Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. The substrate has a trench. First and second doped regions are provided proximate the upper surface of the substrate. A first source region is provided within the first doped region. A second source region is provided within the second doped region. A gate is provided between the first and second source regions. The gate includes a first portion extending downward into the trench. A depth of the trench is no more than a depth of the first doped region.Type: ApplicationFiled: October 3, 2003Publication date: July 1, 2004Applicant: IXYS CorporationInventors: Vladimir Tsukanov, Nathan Zommer
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Patent number: 6710405Abstract: An active area of a power device comprises active cells having designs that vary depending on where they are located in the active area. Design variations include structural variations and variations in the material used to produce the cells.Type: GrantFiled: January 17, 2001Date of Patent: March 23, 2004Assignee: Ixys CorporationInventors: Nathan Zommer, Vladimir Tsukanov
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Patent number: 6683344Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.Type: GrantFiled: September 6, 2002Date of Patent: January 27, 2004Assignee: IXYS CorporationInventors: Vladimir Tsukanov, Nathan Zommer
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Publication number: 20030067034Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.Type: ApplicationFiled: September 6, 2002Publication date: April 10, 2003Applicant: IXYS CorporationInventors: Vladimir Tsukanov, Nathan Zommer
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Patent number: RE42864Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.Type: GrantFiled: January 17, 2006Date of Patent: October 25, 2011Assignee: IXYS CorporationInventors: Vladimir Tsukanov, Nathan Zommer