Patents by Inventor Vladimir Urazaev

Vladimir Urazaev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9978932
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungjoon Kwon, Sechung Oh, Vladimir Urazaev, Ken Tokashiki, Jongchul Park, Gwang-Hyun Baek, Jaehun Seo, Sangmin Lee
  • Patent number: 9685450
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 9496488
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: November 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungjoon Kwon, Sechung Oh, Vladimir Urazaev, Ken Tokashiki, Jongchul Park, Gwang-Hyun Baek, Jaehun Seo, Sangmin Lee
  • Publication number: 20160197081
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 7, 2016
    Inventors: Ki-Yeon Park, Jae-Hyoung CHOI, Vladimir URAZAEV, Jin-Ha JEONG
  • Publication number: 20160181511
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: HYUNGJOON KWON, SECHUNG OH, VLADIMIR URAZAEV, KEN TOKASHIKI, JONGCHUL PARK, Gwang-Hyun BAEK, Jaehun SEO, SANGMIN LEE
  • Patent number: 9324781
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Publication number: 20150243727
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 9059331
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 16, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 8946712
    Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byung-Duk Yang, Vladimir Urazaev, Sung-Wook Kang
  • Patent number: 8927367
    Abstract: A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsang Jeong, Vladimir Urazaev, Jin Ha Jeong, Changhun Lee
  • Publication number: 20140256112
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 11, 2014
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 8809943
    Abstract: A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Soo Lim, Vladimir Urazaev, Jin Ha Jeong, Hansoo Kim, Heayun Lee
  • Publication number: 20140124881
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 8, 2014
    Inventors: HYUNGJOON KWON, SECHUNG OH, VLADIMIR URAZAEV, KEN TOKASHIKI, JONGCHUL PARK, Gwang-Hyun BAEK, Jaehun SEO, SANGMIN LEE
  • Patent number: 8563951
    Abstract: Exposure systems include a beam generator, which is configured to irradiate source beams in a direction of an object to be exposed by the source beams, along with first and second beam shapers. The first beam shaper, which is disposed proximate the beam generator, has a first aperture therein positioned to pass through the source beams received from the beam generator. The second beam shaper is disposed proximate the first beam shaper. The second beam shaper includes a plate having a second aperture therein, which is positioned to receive the source beams that are passed through the first aperture of the first beam shaper. The second beam shaper further includes a first actuator and a first shift screen mechanically coupled to the first actuator.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Jin-Ha Jeong, Vladimir Urazaev, Hea-Yun Lee
  • Publication number: 20120322182
    Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 20, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Duk YANG, Vladimir URAZAEV, Sung-Wook KANG
  • Publication number: 20120292535
    Abstract: Exposure systems include a beam generator, which is configured to irradiate source beams in a direction of an object to be exposed by the source beams, along with first and second beam shapers. The first beam shaper, which is disposed proximate the beam generator, has a first aperture therein positioned to pass through the source beams received from the beam generator. The second beam shaper is disposed proximate the first beam shaper. The second beam shaper includes a plate having a second aperture therein, which is positioned to receive the source beams that are passed through the first aperture of the first beam shaper. The second beam shaper further includes a first actuator and a first shift screen mechanically coupled to the first actuator.
    Type: Application
    Filed: March 14, 2012
    Publication date: November 22, 2012
    Inventors: Jin Choi, Jin-Ha Jeong, Vladimir Urazaev, Hea-Yun Lee
  • Publication number: 20120273872
    Abstract: A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 1, 2012
    Inventors: Jin-Soo Lim, Vladimir Urazaev, Jin Ha Jeong, Hansoo Kim, Heayun Lee
  • Patent number: 8268412
    Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Duk Yang, Vladimir Urazaev, Sung-Wook Kang
  • Patent number: 8236673
    Abstract: A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Son, Jin-ha Jeong, Jung-ho Kim, Vladimir Urazaev, Jong-hyuk Kang, Sung-woo Hyun
  • Publication number: 20120048356
    Abstract: A doping paste includes an inorganic particle including a phosphorus-containing silicon compound and an organic vehicle, wherein a concentration of phosphorus at an interior portion of the inorganic particle is greater than a concentration of phosphorous at a surface of the inorganic particle.
    Type: Application
    Filed: February 28, 2011
    Publication date: March 1, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Soo JEE, Eun-Sung LEE, Se-Yun KIM, Vladimir URAZAEV, Jung Yun WON, Mi-Jeong SONG