Patents by Inventor Vladimir V. Voronkov

Vladimir V. Voronkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for stressing semiconductor substrates
    Patent number: 11764071
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 19, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Apparatus for stressing semiconductor substrates
    Patent number: 11282715
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Apparatus for stressing semiconductor substrates
    Patent number: 11276583
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Apparatus for stressing semiconductor substrates
    Patent number: 11276582
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • APPARATUS FOR STRESSING SEMICONDUCTOR SUBSTRATES
    Publication number: 20190333778
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 31, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • APPARATUS FOR STRESSING SEMICONDUCTOR SUBSTRATES
    Publication number: 20190311912
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • APPARATUS FOR STRESSING SEMICONDUCTOR SUBSTRATES
    Publication number: 20190311913
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • APPARATUS FOR STRESSING SEMICONDUCTOR SUBSTRATES
    Publication number: 20190295853
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Apparatus for stressing semiconductor substrates
    Patent number: 10361097
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 23, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
    Patent number: 9634098
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 25, 2017
    Assignee: SunEdison Semiconductor Ltd. (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Processes and apparatus for preparing heterostructures with reduced strain by radial compression
    Patent number: 9583364
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Processes and apparatus for preparing heterostructures with reduced strain by radial distension
    Patent number: 9583363
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei
    Patent number: 9129919
    Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 8, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Processes for suppressing minority carrier lifetime degradation in silicon wafers
    Patent number: 8969119
    Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 3, 2015
    Assignee: MEMC Singapore Pte. Ltd. (UEN200614794D)
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • OXYGEN PRECIPITATION IN HEAVILY DOPED SILICON WAFERS SLICED FROM INGOTS GROWN BY THE CZOCHRALSKI METHOD
    Publication number: 20140361408
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Processes and Apparatus for Preparing Heterostructures with Reduced Strain by Radial Distension
    Publication number: 20140187022
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SUNEDISON, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Apparatus for Stressing Semiconductor Substrates
    Publication number: 20140182788
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Processes and Apparatus for Preparing Heterostructures with Reduced Strain by Radial Compression
    Publication number: 20140187023
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • PRODUCTION OF HIGH PRECIPITATE DENSITY WAFERS BY ACTIVATION OF INACTIVE OXYGEN PRECIPITATE NUCLEI
    Publication number: 20140141537
    Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: SUNEDISON, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS
    Publication number: 20130102129
    Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
    Type: Application
    Filed: June 1, 2012
    Publication date: April 25, 2013
    Applicant: MEMC SINGAPORE PTE. LTD. (UEN200614794D)
    Inventors: Robert J. Falster, Vladimir V. Voronkov