Abstract: A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state.

Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

Abstract: Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460).

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460).

Abstract: A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state.

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input.

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139).

Abstract: A time to digital converter (10) is disclosed.