Patents by Inventor Vladislav Kopzon
Vladislav Kopzon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220414046Abstract: Systems, devices, computer program products, and methods include determining by a connection manager that a connected device can be enhanced by an asymmetrical multi-lane link. The connection manager can use system parameters, including bandwidth information, to switch a direction of one or more lanes of the multi-lane link. The connection manager can use register setting instructions to change register settings on the host side and on the device side to switch the direction of one or more lanes of the multi-lane link.Type: ApplicationFiled: August 26, 2022Publication date: December 29, 2022Applicant: Intel CorporationInventors: Vladislav Kopzon, Reuven Rozic
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Publication number: 20220345289Abstract: The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Inventors: Ehud Shoor, Tsion Vidal, Vladislav Kopzon, Uri Hermoni, Golan Cohen, Efraim Kugman, Ziv Kabiry
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Patent number: 11474967Abstract: Systems, devices, computer program products, and methods include determining by a connection manager that a connected device can be enhanced by an asymmetrical multi-lane link. The connection manager can use system parameters, including bandwidth information, to switch a direction of one or more lanes of the multi-lane link. The connection manager can use register setting instructions to change register settings on the host side and on the device side to switch the direction of one or more lanes of the multi-lane link.Type: GrantFiled: June 25, 2018Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Vladislav Kopzon, Reuven Rozic
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Publication number: 20200327041Abstract: A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Gilad Shayevitz, Tsvika Kurts, Vladislav Kopzon, Reuven Rozic, Yaniv Hayat
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Publication number: 20190050365Abstract: Systems, devices, computer program products, and methods include determining by a connection manager that a connected device can be enhanced by an asymmetrical multi-lane link. The connection manager can use system parameters, including bandwidth information, to switch a direction of one or more lanes of the multi-lane link. The connection manager can use register setting instructions to change register settings on the host side and on the device side to switch the direction of one or more lanes of the multi-lane link.Type: ApplicationFiled: June 25, 2018Publication date: February 14, 2019Applicant: Intel CorporationInventors: Vladislav Kopzon, Reuven Rozic
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Patent number: 9225673Abstract: A method and apparatus to reduce memory required in a network interface controller to store per flow state information associated with a network connection is provided. Instead of storing per flow state information for a connection in the network interface controller at an endpoint of the connection, the per flow state information for the connection is stored in memory external to the network interface controller. The stored state information is conveyed in a packet by the network interface controller between the endpoints of the connection. For a Transmission Control Protocol (TCP) connection, the state information is conveyed between the endpoints of the TCP connection in a TCP option included in the TCP header in the packet.Type: GrantFiled: August 7, 2012Date of Patent: December 29, 2015Assignee: INTEL CORPORATIONInventors: Ben-Zion Friedman, Eliel Louzoun, Eliezer Tamir, Vladislav Kopzon
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Patent number: 8917740Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: GrantFiled: November 15, 2013Date of Patent: December 23, 2014Inventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Publication number: 20140092915Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: ApplicationFiled: November 15, 2013Publication date: April 3, 2014Applicant: NET NAVIGATION SYSTEMS, LLCInventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Patent number: 8599870Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: GrantFiled: September 3, 2012Date of Patent: December 3, 2013Inventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Publication number: 20120327951Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: ApplicationFiled: September 3, 2012Publication date: December 27, 2012Inventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Publication number: 20120300633Abstract: A method and apparatus to reduce memory required in a network interface controller to store per flow state information associated with a network connection is provided. Instead of storing per flow state information for a connection in the network interface controller at an endpoint of the connection, the per flow state information for the connection is stored in memory external to the network interface controller. The stored state information is conveyed in a packet by the network interface controller between the endpoints of the connection. For a Transmission Control Protocol (TCP) connection, the state information is conveyed between the endpoints of the TCP connection in a TCP option included in the TCP header in the packet.Type: ApplicationFiled: August 7, 2012Publication date: November 29, 2012Inventors: Ben-Zion Friedman, Eliel Louzoun, Eliezer Tamir, Vladislav Kopzon
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Patent number: 8259738Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: GrantFiled: May 1, 2007Date of Patent: September 4, 2012Assignee: Net Navigation Systems, LLCInventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Patent number: 8259582Abstract: A method and apparatus to reduce memory required in a network interface controller to store per flow state information associated with a network connection is provided. Instead of storing per flow state information for a connection in the network interface controller at an endpoint of the connection, the per flow state information for the connection is stored in memory external to the network interface controller. The stored state information is conveyed in a packet by the network interface controller between the endpoints of the connection. For a Transmission Control Protocol (TCP) connection, the state information is conveyed between the endpoints of the TCP connection in a TCP option included in the TCP header in the packet.Type: GrantFiled: November 13, 2009Date of Patent: September 4, 2012Assignee: Intel CorporationInventors: Ben-Zion Friedman, Eliel Louzoun, Eliezer Tamir, Vladislav Kopzon
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Publication number: 20110116375Abstract: A method and apparatus to reduce memory required in a network interface controller to store per flow state information associated with a network connection is provided. Instead of storing per flow state information for a connection in the network interface controller at an endpoint of the connection, the per flow state information for the connection is stored in memory external to the network interface controller. The stored state information is conveyed in a packet by the network interface controller between the endpoints of the connection. For a Transmission Control Protocol (TCP) connection, the state information is conveyed between the endpoints of the TCP connection in a TCP option included in the TCP header in the packet.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Inventors: Ben-Zion Friedman, Eliel Louzoun, Eliezer Tamir, Vladislav Kopzon
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Publication number: 20080273545Abstract: A system and method are provided for prioritizing network processor information flow in a channel service manager (CSM). The method receives a plurality of information streams on a plurality of input channels, and selectively links input channels to CSM channels. The information streams are stored, and the stored the information streams are mapped to a processor queue in a group of processor queues. Information streams are supplied from the group of processor queues to a network processor in an order responsive to a ranking of the processor queues inside the group. More explicitly, selectively linking input channels to CSM channels includes creating a fixed linkage between each input port and an arbiter in a group of arbiters, and scheduling information streams in response to the ranking of the arbiter inside the group. Finally, a CSM channel is selected for each information stream scheduled by an arbiter.Type: ApplicationFiled: May 1, 2007Publication date: November 6, 2008Inventors: Alexander Sgouros, Vladislav Kopzon, Noam Halevy
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Patent number: 6189061Abstract: A multi-master bus system (10) comprises bus (12), a plurality of bus devices (14, 16, 18, 20, 22, 24), coupled to the bus, including masters (14, 16, 18), and slaves (20, 22, 24), a memory controller (26) for controlling the data exchange on bus (12), having a memory (36) for storing a transaction type value with respect to each slave (20, 22, 24). The multi-master bus system (10) comprises further an arbiter (30) for performing bus arbitration, arbiter (30) having logic for conditionally subsequently granting the bus (12) to a master of an initiating transaction for a closing transaction depending on the transaction type value of the slave of the initiating transaction. The multi-master bus system makes atomic or indivisible transactions possible on a bus without changing the bus width or the bus protocol.Type: GrantFiled: February 1, 1999Date of Patent: February 13, 2001Assignee: Motorola, Inc.Inventors: Itai Katz, Moti Kurnick, Noam Halevi, Vladislav Kopzon