Patents by Inventor Vladislav Y. Vassiliev

Vladislav Y. Vassiliev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6583069
    Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: June 24, 2003
    Assignee: Chartered Semiconductor Manufacturing Co., Ltd.
    Inventors: Vladislav Y. Vassiliev, John Leonard Sudijono
  • Patent number: 6027982
    Abstract: A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: February 22, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Igor V. Peidous, Vladislav Y. Vassiliev, Chock H. Gan, Guang Ping Hua
  • Patent number: 5876798
    Abstract: Films of fluorinated silicon oxide, suitable for use as inter-metal dielectrics, have been deposited by means of CVD at reduced pressure using fluorotriethoxysilane (FTES) and tetra-exthyloxysilane (TEOS) as the precursors, together with ozone (mixed with oxygen). If tight control over the deposition conditions is exercised, high quality films having no surface damage and good step coverage, with no trapped voids, can be obtained. In a second embodiment of the invention, the TEOS is omitted and only FTES is used. Among the most important deposition parameters we include temperature at 400-500.degree. C., pressure at 200-260 torr, ozone concentration (in oxygen) 8-12%, and an ozone:precursor ratio of 3-10 to 1 weight percent. In a third embodiment, a stacked layer is formed, consisting of at least one fluorinated silicon oxide layer and one silicon dioxide layer, deposited within the same deposition process by changing the TEOS or the FTES flow.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: March 2, 1999
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Vladislav Y. Vassiliev