Patents by Inventor Vojislav Protic
Vojislav Protic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8593345Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: GrantFiled: February 20, 2012Date of Patent: November 26, 2013Assignee: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
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Publication number: 20120313817Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: ApplicationFiled: February 20, 2012Publication date: December 13, 2012Applicant: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan A. Dasannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
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Patent number: 8321636Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: GrantFiled: March 6, 2006Date of Patent: November 27, 2012Assignee: CSR Technology Inc.Inventors: Nicolas P. Vantalon, Steven A. Gronemeyer, Vojislav Protic
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Patent number: 8138972Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: GrantFiled: September 2, 2004Date of Patent: March 20, 2012Assignee: CSR Technology Inc.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan A. Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
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Publication number: 20110102258Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at last one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.Type: ApplicationFiled: September 2, 2004Publication date: May 5, 2011Applicant: SIRF TECHNOLOGY, INC.Inventors: Paul A. Underbrink, Henry D. Falk, Steven A. Gronemeyer, Chittharanjan Dassannacharya, Charles P. Norman, Nicolas Vantalon, Vojislav Protic
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Publication number: 20060248289Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: ApplicationFiled: March 6, 2006Publication date: November 2, 2006Inventors: Nicolas Vantalon, Steven Gronemeyer, Vojislav Protic
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Patent number: 7047368Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: GrantFiled: October 28, 2003Date of Patent: May 16, 2006Assignee: SiRF Technology, Inc.Inventors: Nicolas P. Vantalon, Steven A. Gronemeyer, Vojislav Protic
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Publication number: 20050050282Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.Type: ApplicationFiled: October 28, 2003Publication date: March 3, 2005Inventors: Nicolas Vantalon, Steven Gronemeyer, Vojislav Protic